SBVS188E march   2012  – may 2023 TPS7A16-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Regulated Output (VOUT)
      3. 7.3.3 PG Delay Timer (DELAY)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Good
      2. 7.4.2 Power-Good Delay and Delay Capacitor
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS7A1601-Q1 Circuit as an Adjustable Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Adjustable Voltage Operation
          2. 8.2.1.2.2 Resistor Selection
          3. 8.2.1.2.3 Capacitor Recommendations
          4. 8.2.1.2.4 Input and Output Capacitor Requirements
          5. 8.2.1.2.5 Feed-Forward Capacitor (Only for Adjustable Version)
          6. 8.2.1.2.6 Transient Response
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Automotive Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Device Recommendations
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Multicell Battery Packs
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
      4. 8.2.4 Battery-Operated Power Tools
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Additional Layout Considerations
        2. 8.4.1.2 Power Dissipation
        3. 8.4.1.3 Thermal Considerations
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2 Power-Good Delay and Delay Capacitor

The power-good delay time (tDELAY) is defined as the time period from when VOUT exceeds the PG trip threshold voltage (VIT) to when the PG output is high. This power-good delay time is set by an external capacitor (CDELAY) connected from the DELAY pin to GND; this capacitor is charged from 0 V to approximately 1.8 V by the DELAY pin current (IDELAY) when VOUT exceeds the PG trip threshold (VIT).

When CDELAY is used, the PG output is high-impedance when VOUT exceeds VIT, and VDELAY exceeds VREF.

The power-good delay time can be calculated using: tDELAY = (CDELAY × VREF) / IDELAY. For example, when CDELAY = 10 nF, the PG delay time is approximately 12 ms; that is, (10 nF × 1.193 V) / 1 μA = 11.93 ms.