SBVS342A February   2019  – March 2019 TPS7A16A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Regulated Output (VOUT)
      3. 7.3.3 PG Delay Timer (DELAY)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Good
        1. 7.4.1.1 Power-Good Delay and Delay Capacitor
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS7A16A-Q1 Circuit as an Adjustable Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Adjustable Voltage Operation
            1. 8.2.1.2.1.1 Resistor Selection
          2. 8.2.1.2.2 Capacitor Recommendations
          3. 8.2.1.2.3 Input and Output Capacitor Requirements
          4. 8.2.1.2.4 Feed-Forward Capacitor (Only for Adjustable Version)
          5. 8.2.1.2.5 Transient Response
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Automotive Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Device Recommendations
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Additional Layout Considerations
      2. 10.1.2 Power Dissipation
      3. 10.1.3 Thermal Considerations
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA= –40°C to +125°C, VIN = VOUT(NOM) + 500 mV or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 2.2 μF, COUT = 2.2 μF, and FB tied to OUT (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 3 60 V
VREF Internal reference TA = 25°C, VFB = VREF, VIN = 3 V, IOUT = 10 μA 1.169 1.193 1.217 V
VUVLO Undervoltage lockout threshold 2 V
VOUT Output voltage range VIN ≥ VOUT(NOM) + 0.5 V VREF 18.5 V
Overall VOUT accuracy VOUT(NOM) + 0.5 V ≤ VIN ≤ 60 V(1),
10 µA ≤ IOUT ≤ 100 mA		 –2% 2%
ΔVO(ΔVI) Line regulation 3 V ≤ VIN ≤ 60 V  ±1 %VOUT
ΔVO(ΔIO) Load regulation 10 µA ≤ IOUT ≤ 100 mA ±1 %VOUT
VDO Dropout voltage VIN = 0.95xVOUT(NOM), IOUT = 20 mA 60 mV
VIN = 0.95xVOUT(NOM), IOUT = 100 mA 265 500
ILIM Current limit VOUT = 90% VOUT(NOM), VIN = VOUT(NOM) + 1 V(3) 101 225 400 mA
VOUT = 90% VOUT(NOM), VIN = 3 V(4) 101 225 400
IGND Ground current 3 V ≤ VIN ≤ 60 V, IOUT = 10 µA 5 15 μA
IOUT = 100 mA, VOUT = 1.2 V 60
ISHDN Shutdown supply current VEN = 0.4 V, VIN = 12 V 0.59 5.0 μA
I FB Feedback current(2) –1 0.0 1 µA
IEN Enable current 3 V ≤ VIN ≤ 12 V, VIN = VEN –1 0.01 1 μA
VEN_HI Enable high-level voltage 1.2 V
VEN_LO Enable low-level voltage 0.3 V
VIT PG trip threshold OUT pin floating, VFB increasing, VIN ≥ VIN_MIN 85 95 %VOUT
OUT pin floating, VFB decreasing, VIN ≥ VIN_MIN 83 93
VHYS PG trip hysteresis 2.3 %VOUT
VPG, LO PG output low voltage OUT pin floating, VFB = 80% VREF, IPG = 100 µA 0.4 V
IPG, LKG PG leakage current VPG = VOUT(NOM) –1 1 μA
IDELAY DELAY pin current 1 2 μA
PSRR Power-supply rejection ratio VIN = 3 V, VOUT(NOM) = VREF, COUT = 10 μF,
f = 100 Hz		 50 dB
TSD Thermal shutdown temperature Shutdown, temperature increasing 175 °C
Reset, temperature decreasing 155
(1) Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈ (VIN – VOUT) × IOUT =
(24 V – VREF) × 50 mA ≈ 1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as the power dissipated is within the thermal limits of the package plus any external heatsinking.
(2) IFB > 0 µA flows out of the device.
(3) For fixed output voltages only.
(4) For adjustable output only, where VOUT = 1.2 V