SBVS457A August   2024  – September 2024 TPS7A20U

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Low Output Noise
      2. 6.3.2 Smart Enable
      3. 6.3.3 Dropout Voltage
      4. 6.3.4 Current Limit
      5. 6.3.5 Undervoltage Lockout (UVLO)
      6. 6.3.6 Thermal Shutdown
      7. 6.3.7 Active Discharge
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Recommended Capacitor Types
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Load Transient Response
      4. 7.1.4 Undervoltage Lockout (UVLO) Operation
      5. 7.1.5 Power Dissipation (PD)
        1. 7.1.5.1 Estimating Junction Temperature
        2. 7.1.5.2 Recommended Area for Continuous Operation
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YCK|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Description

The TPS7A20U is an ultra-small, low-dropout (LDO) linear regulator that sources 75mA of output current. The TPS7A20U is designed to provide low noise, high PSRR, and excellent load and line transient performance. This performance meets the requirements of RF and other sensitive analog circuits. Using innovative design techniques, the TPS7A20U offers ultra-low noise performance without the addition of a noise bypass capacitor. The TPS7A20U also provides the advantage of low quiescent current, which is designed for battery-powered applications. With a 1.6V to 6.0V input voltage range and a 0.8V to 5.5V output range, the TPS7A20U is applicable for a wide variety of applications. The device uses a precision reference circuit to provide a maximum accuracy of 1.5% over load, line, and temperature variations.

The TPS7A20U features an internal soft-start to lower the inrush current, thus minimizing the input voltage drop during start-up. The device is stable with small ceramic capacitors, allowing for a small overall solution size.

The TPS7A20U has a smart enable input circuit with an internally controlled pulldown resistor that keeps the LDO disabled. The LDO remains disabled even when the EN pin is left floating and helps eliminate the external components used to pulldown the EN pin.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
TPS7A20U YCK (DSBGA, 4) 0.616mm × 0.616mm
For more information, see the Mechanical, Packaging, and Orderable Information.
The package size (length × width) is a nominal value and includes pins, where applicable.

 

TPS7A20U Simplified Application Schematic Simplified Application Schematic