Layout is a critical part of good power-supply design. Several signal paths that conduct fast-changing currents or voltages can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with a X5R or X7R dielectric.

10.1 Layout Guidelines

10.2 Layout Example

It may be possible to obtain acceptable performance with alternative PCB layouts; however, the layout shown in Figure 41 and the schematic shown in Figure 42 have been shown to produce good results and are meant as a guideline.

Figure 40. TPS7A33 5-mm × 5-mm QFN-20 Layout Guideline

Figure 41. TPS7A33 TO-220 EVM PCB Layout Example: Top Layer

Figure 42. TPS7A33 TO-220 EVM PCB Layout Example: Bottom Layer

Figure 43. Schematic for TPS7A33 TO-220 EVM PCB Layout Example

10.3 Thermal Performance and Heat Sink Selection

The primary TPS7A33 application is to provide ultralow-noise voltage rails to high-performance analog circuitry in order to maximize system accuracy and precision. The high-current and high-voltage characteristics of this regulator means that, often enough, high power (heat) is dissipated from the device itself. This heat, if dissipated into the PCB (as is the case with SMT packages), creates a temperature gradient in the surrounding area that causes nearby components to react to this temperature change (drift). In high-performance systems, such drift may degrade overall system accuracy and precision.

Compared to surface-mount packages, the TO-220 (KC) package allows for an external heat sink to be used to maximize thermal performance and keep heat from dissipating into the PCB.

The heat generated by the device is a result of the power dissipation, which depends on input voltage and load conditions. Power dissipation (P_D) can be approximated by calculating the product of the output current times the voltage drop across the output pass element, as shown in Equation 4:

Equation 4.

Heat flows from the device to the ambient air through many paths, each of which represents resistance to the heat flow; this effect is called thermal resistance.

The total thermal resistance of a system is defined by: θ_JA = (T_J – T_A)/P_D; where: θ_JA is the thermal resistance (in °C/W), T_J is the allowable juntion temperature of the device (in °C), T_A is the maximum temperature of the ambient cooling air (in °C), and P_D is the amount of power (heat) dissipated by the device (in W).

Whenever a heat sink is installed, the total thermal resistance (θ_JA) is the sum of all the individual resistances from the device, going through its case and heatsink to the ambient cooling air (θ_JA = θ_JC + θ_CS + θ_SA). Realistically, only two resistances can be controlled: θ_CS and θ_SA. Therefore, for a device with a known θ_JC, θ_CS and θ_SA become the main design variables in selecting a heat sink.

The thermal interface between the case and the heat sink (θ_CS) is controlled by selecting the correct heat-conducting material. Once the θ_CS is selected, the required thermal resistance from the heat sink to ambient is calculated by the following equation: θ_SA = [(T_J – T_A)/P_D] – [θ_JC+ θ_CS]. This information allows the most appropriate heat sink to be selected for any particular application.

10.4 Package Mounting

The TO-220 (KC) 7-lead, straight-formed package lead spacing poses a challenge when creating a suitable PCB footprint without bending the leads. Component forming pliers can be used to manually bend the package leads into a 7-lead stagger pattern with increased lead spacing that can be more easily used.

The TPS7A33 evaluation board layout can be used as a guideline on suitable PCB footprints, available at www.ti.com. Refer to the TPS7A3301EVM-061 user's guide for more information.