8.1.1 Adjustable Operation

The TPS7A3401 device has an output voltage range from –1.174 V to –18 V. The nominal output voltage of the device is set by two external resistors, as shown in Figure 19.

Figure 19. Adjustable Operation for Maximum AC Performance

R₁ and R₂ can be calculated for any output voltage range using the formula shown in Equation 1. To ensure stability under no load conditions, this resistive network must provide a current equal to or greater than 5 μA.

Equation 1.

If greater voltage accuracy is required, consider the output voltage offset contributions because of the feedback pin current and use 0.1% tolerance resistors.

8.1.2 Transient Response

As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases duration of the transient response.

8.1.3 Post DC-DC Converter Filtering

Most of the time, the voltage rails available in a system do not match the voltage specifications demanded by one or more of its circuits; these rails must be stepped up or down, depending on specific voltage requirements.

DC-DC converters are the preferred solution to step up or down a voltage rail when current consumption is not negligible. They offer high-efficiency with minimum heat generation, but they have one primary disadvantage: they introduce a high-frequency component, and the associated harmonics, on top of the DC output signal.

This high-frequency component, if not filtered properly, degrades analog circuitry performance, reducing overall system accuracy and precision.

The TPS7A3401 device offers a wide-bandwidth, very high power-supply rejection ratio. This specification makes it ideal for post DC-DC converter filtering, as shown in Figure 20. TI highly recommends using the maximum performance schematic shown in Figure 19. Also, verify that the fundamental frequency (and its first harmonic, if possible) is within the bandwidth of the regulator PSRR, shown in Figure 15.

Figure 20. Post DC-DC Converter Regulation to High-Performance Analog Circuitry

8.1.4 Power for Precision Analog

One of the primary applications of the TPS7A3401 device is to provide ultralow-noise voltage rails to high-performance analog circuitry to maximize system accuracy and precision.

The TPS7A3401 negative high-voltage linear regulator provides ultralow noise positive and negative voltage rails to high-performance analog circuitry, such as operational amplifiers, ADCs, DACs, and audio amplifiers.

Because of the ultralow noise levels at high voltages, analog circuitry with high-voltage input supplies can be used. This characteristic allows for high-performance analog solutions to optimize the voltage range, maximizing system accuracy.

8.2.1 Design Requirements

The design goals are V_IN = –3 V, V_OUT = –1.2 V, and I_OUT = 150 mA, maximum. The input supply comes from a supply on the same printed-circuit-board (PCB). The design circuit is shown in Figure 19.

The design space consists of C_IN, C_OUT, C_FF, R₁, and R₂, at T_A(max) = 75°C.

8.2.2 Detailed Design Procedure

The first step when designing with a linear regulator is to examine the maximum load current along with the input and output voltage requirements to determine if the device thermal and dropout voltage requirements can be met. At 150 mA, the input dropout voltage of the TPS7A3401 family is a maximum of 800 mV over temperature; therefore, the dropout headroom of 1.8 V is sufficient for operation over both input and output voltage accuracy. Dropout headroom is calculated as V_IN – V_OUT – V_DO(max), and should be greater than 0 for reliable operation. V_DO(max) is the maximum dropout allowed, given worst-case load conditions.

The maximum power dissipated in the linear regulator is the maximum voltage dropped across the pass element from the input to the output, multiplied by the maximum load current. In this example, the maximum voltage drop across in the pass element is |3 V – 1.2 V|, giving us a V_DO = 1.8 V. The power dissipated in the pass element is calculated by taking this voltage drop multiplied by the maximum load current. For this example, the maximum power dissipated in the linear regulator is 0.273 W, and is calculated using Equation 2.

Once the power dissipated in the linear regulator is known, the corresponding junction temperature rise can be calculated. To calculate the junction temperature rise above ambient, the power dissipated must be multiplied by the junction-to-ambient thermal resistance. This calculation gives the worst-case junction temperature; good thermal design can significantly reduce this number. For thermal resistance information, refer to Thermal Information. For this example, using the DGN package, the maximum junction temperature rise is calculated to be 17.3°C. The maximum junction temperature rise is calculated by adding junction temperature rise to the maximum ambient temperature, which is 75°C for this example. For this example, the designer calculates the maximum junction temperature is 92.3°C. Keep in mind the maximum junction temperate must be less than 125°C for reliable device operation. Additional ground planes, added thermal vias, and air flow all help to lower the maximum junction temperature.

Use the following equations to pick the rest of the components:

To ensure stability under no-load conditions, the current through the resistor network must be greater than 5 µA, as shown in Equation 3.

Equation 3.

To set R₂ = 100 kΩ for a standard 1% value resistor, we calculate R₁ as shown in Equation 4.

Equation 4.

Use a standard, 1%, 2.05-kΩ resistor for R₁.

For C_IN, assume that the –3-V supply has some inductance, and is placed several inches away from the PCB. For this case, we select a 2.2-µF ceramic input capacitor to ensure that the input impedance is negligible to the LDO control loop while keep the physical size and cost of the capacitor low; this component is a common-value capacitor.

For better PSRR for this design, use a 10-µF input and output capacitor. To reduce the peaks from transients but slow down the recovery time, increase the output capacitor size or add additional output capacitors.

8.2.3 Application Curves

Figure 22. Line Regulation

Figure 23. Load Regulation