The TPS7A4001 device is a very high voltage-tolerant linear regulator that offers the benefits of a thermally-enhanced package (HVSSOP), and is able to withstand continuous DC or transient input voltages of up to 100 V.
The TPS7A4001 device is stable with any output capacitance greater than 4.7 µF and any input capacitance greater than 1 µF (over temperature and tolerance). Therefore, implementations of this device require minimal board space because of its miniaturized packaging (HVSSOP) and a potentially small output capacitor. In addition, the TPS7A4001 device offers an enable pin (EN) compatible with standard CMOS logic to enable a low-current shutdown mode.
The TPS7A4001 device has an internal thermal shutdown and current limiting to protect the system during fault conditions. The HVSSOP packages has an operating temperature range of TJ = –40°C to 125°C.
In addition, the TPS7A4001 device is ideal for generating a low-voltage supply from intermediate voltage rails in telecom and industrial applications; not only can it supply a well-regulated voltage rail, but it can also withstand and maintain regulation during very high and fast voltage transients. These features translate to simpler and more cost-effective electrical surge-protection circuitry for a wide range of applications, including PoE, bias supply, and LED lighting.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS7A4001 | HVSSOP (8) | 3.00 mm × 5.00 mm |
Changes from A Revision (March 2011) to B Revision
Changes from * Revision (March 2011) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
OUT | 1 | O | Regulator output. A capacitor > 4.7 µF must be tied from this pin to ground to assure stability. |
FB | 2 | O | This pin is the input to the control-loop error amplifier. It is used to set the output voltage of the device. |
NC | 3 | — | Not internally connected. This pin must either be left open or tied to GND. |
6 | |||
7 | |||
GND | 4 | — | Ground |
EN | 5 | I | This pin turns the regulator on or off. If VEN ≥ VEN_HI the regulator is enabled. If VEN ≤ VEN_LO, the regulator is disabled. If not used, the EN pin can be connected to IN. Make sure that VEN ≤ VIN at all times. |
IN | 8 | I | Input supply |
PowerPAD | — | — | Solder to printed-circuit-board (PCB) to enhance thermal performance. NOTE: The PowerPAD is internally connected to GND. Although it can be left floating, TI highly recommends connecting the PowerPAD to the GND plane. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | IN pin to GND pin | –0.3 | 105 | V |
OUT pin to GND pin | –0.3 | 105 | ||
OUT pin to IN pin | –105 | 0.3 | ||
FB pin to GND pin | –0.3 | 2 | ||
FB pin to IN pin | –105 | 0.3 | ||
EN pin to IN pin | –105 | 0.3 | ||
EN pin to GND pin | –0.3 | 105 | ||
Current | Peak output | Internally limited | ||
Temperature | Operating virtual junction, TJ | –40 | 125 | °C |
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | 7 | 100 | V | ||
VOUT | 1.161 | 90 | V | ||
VEN | 0 | 100 | V | ||
IOUT | 0 | 50 | mA |
THERMAL METRIC(1) | TPS7A4001 | UNIT | |
---|---|---|---|
DGN (HVVSOP) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 66.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 54.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 38.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 2 | °C/W |
ψJB | Junction-to-board characterization parameter | 37.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 15.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
VIN | Input voltage | 7 | 100 | V | ||||
VREF | Internal reference | TJ = 25°C, VFB = VREF, VIN = 9 V, IOUT = 25 mA | 1.161 | 1.173 | 1.185 | V | ||
VOUT | Output voltage range(1) | VIN ≥ VOUT(NOM) + 2 V | VREF | 90 | V | |||
Nominal accuracy | TJ = 25°C, VIN = 9 V, IOUT = 25 mA | –1 | 1 | %VOUT | ||||
Overall accuracy | VOUT(NOM) + 2 V ≤ VIN ≤ 24 V(2)
100 µA ≤ IOUT ≤ 50 mA |
–2.5 | 2.5 | %VOUT | ||||
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Line regulation | 7 V ≤ VIN ≤ 100 V | 0.03 | %VOUT | ||||
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Load regulation | 100 µA ≤ IOUT ≤ 50 mA | 0.31 | %VOUT | ||||
VDO | Dropout voltage | VIN = 17 V, VOUT(NOM) = 18 V, IOUT = 20 mA | 290 | mV | ||||
VIN = 17 V, VOUT(NOM) = 18 V, IOUT = 50mA | 0.78 | 1.3 | V | |||||
ILIM | Current limit | VOUT = 90% VOUT(NOM), VIN = 7 V, TJ ≤ 85°C | 51 | 117 | 200 | mA | ||
VOUT = 90% VOUT(NOM), VIN = 9 V | 51 | 128 | 200 | mA | ||||
IGND | Ground current | 7 V ≤ VIN ≤ 100 V, IOUT = 0 mA | 25 | 65 | μA | |||
IOUT = 50 mA | 25 | μA | ||||||
ISHDN | Shutdown supply current | VEN = 0.4 V | 4.1 | 20 | μA | |||
IFB | Feedback current(3) | –0.1 | 0.01 | 0.1 | µA | |||
IEN | Enable current | 7 V ≤ VIN ≤ 100 V, VIN = VEN | 0.02 | 1 | μA | |||
VEN_HI | Enable high-level voltage | 1.5 | VIN | V | ||||
VEN_LO | Enable low- level voltage | 0 | 0.4 | V | ||||
VNOISE | Output noise voltage | VIN = 12 V, VOUT(NOM) = VREF, COUT = 10 μF, BW = 10 Hz to 100 kHz |
58 | μVRMS | ||||
VIN = 12 V, VOUT(NOM) = 5 V, COUT = 10 μF, CBYP(4) = 10 nF, BW = 10 Hz to 100 kHz | 73 | μVRMS | ||||||
PSRR | Power-supply rejection ratio | VIN = 12 V, VOUT(NOM) = 5 V, COUT = 10 μF, CBYP(4) = 10 nF, ƒ = 100 Hz | 65 | dB | ||||
TSD | Thermal shutdown temperature | Shutdown, temperature increasing | 170 | °C | ||||
Reset, temperature decreasing | 150 | °C | ||||||
TJ | Operating junction temperature | –40 | 125 | °C |