The TPS7A47 is a family of positive voltage (+36 V), ultralow-noise (4 µVRMS) low-dropout linear regulators (LDO) capable of sourcing a 1-A load.
The TPS7A4700 output voltages are user-programmable (up to 20.5 V) using a printed circuit board (PCB) layout without the need of external resistors or feed-forward capacitors, thus reducing overall component count.
The TPS7A4701 output voltage can be configured with a user-programmable PCB layout (up to 20.5 V), or adjustable (up to 34 V) with external feedback resistors.
The TPS7A47 is designed with bipolar technology primarily for high-accuracy, high-precision instrumentation applications where clean voltage rails are critical to maximize system performance. This feature makes the device ideal for powering operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other high-performance analog circuitry in critical applications such as medical, radio frequency (RF), and test-and-measurement.
In addition, the TPS7A47 is ideal for post dc-dc converter regulation. By filtering out the output voltage ripple inherent to dc-dc switching conversions, maximum system performance is ensured in sensitive instrumentation, test-and-measurement, audio, and RF applications.
For applications where positive and negative low-noise rails are required, consider TI's TPS7A33 family of negative high-voltage, ultralow-noise linear regulators.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS7A470x | VQFN (20) | 5 mm × 5 mm |
Changes from E Revision (January 2014) to F Revision
Changes from D Revision (December 2013) to E Revision
Changes from C Revision (July 2013) to D Revision
Changes from B Revision (April 2013) to C Revision
Changes from A Revision (July 2012) to B Revision
Changes from * Revision (June 2012) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
0P1V | 12 | I | When connected to GND, this pin adds 0.1 V to the nominal output voltage of the regulator. |
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating. | |||
0P2V | 11 | I | When connected to GND, this pin adds 0.2 V to the nominal output voltage of the regulator. |
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating. | |||
0P4V | 10 | I | When connected to GND, this pin adds 0.4 V to the nominal output voltage of the regulator. |
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating. | |||
0P8V | 9 | I | When connected to GND, this pin adds 0.8 V to the nominal output voltage of the regulator. |
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating. | |||
1P6V | 8 | I | When connected to GND, this pin adds 1.6 V to the nominal output voltage of the regulator. |
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating. | |||
3P2V | 6 | I | When connected to GND, this pin adds 3.2 V to the nominal output voltage of the regulator. |
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating. | |||
6P4V1 | 5 | I | When connected to GND, this pin adds 6.4 V to the nominal output voltage of the regulator. |
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating. | |||
6P4V2 | 4 | I | When connected to GND, this pin adds 6.4 V to the nominal output voltage of the regulator. |
Do not connect any voltage other than GND to this pin. If not used, leave this pin floating. | |||
EN | 13 | I | Enable pin. The device is enabled when the voltage on this pin exceeds the maximum enable voltage, VEN(HI). If enable is not required, tie EN to IN. |
GND | 7 | — | Ground |
IN | 15, 16 | I | Input supply. A capacitor greater than or equal to 1 µF must be tied from this pin to ground to assure stability. A 10-µF capacitor is recommended to be connected from IN to GND (as close to the device as possible) to reduce circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedances are encountered. |
NC | 2, 17-19 | — | This pin can be left open or tied to any voltage between GND and IN. |
NR | 14 | — | Noise reduction pin. When a capacitor is connected from this pin to GND, RMS noise can be reduced to very low levels. A capacitor greater than or equal to 10 nF must be tied from this pin to ground to assure stability. A 1-µF capacitor is recommended to be connected from NR to GND (as close to the device as possible) to maximize ac performance and minimize noise. |
OUT | 1, 20 | O | Regulator output. A capacitor greater than or equal to 10 µF must be tied from this pin to ground to assure stability. A 47-µF ceramic output capacitor is highly recommended to be connected from OUT to GND (as close to the device as possible) to maximize ac performance. |
SENSE/FB | 3 | I | Control-loop error amplifier input (TPS7A4701 only). |
This is the SENSE pin if the device output voltage is programmed using ANY-OUT (no external feedback resistors). This pin must be connected to OUT. Connect this pin to the point of load to maximize accuracy. | |||
This is the FB pin if the device output voltage is set using external resistors. See the Adjustable Operation section for more details. | |||
SENSE | 3 | I | Control-loop error amplifier input (TPS7A4700 only). |
This is the SENSE pin of the device and must be connected to OUT. Connect this pin to the point of load to maximize accuracy. | |||
Thermal Pad | — | Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Voltage(2) | IN pin to GND pin | –0.4 | +36 | V | |
EN pin to GND pin | –0.4 | +36 | V | ||
EN pin to IN pin | –36 | +0.4 | V | ||
OUT pin to GND pin | –0.4 | +36 | V | ||
NR pin to GND pin | –0.4 | +36 | V | ||
SENSE/FB pin to GND pin | –0.4 | +36 | V | ||
0P1V pin to GND pin | –0.4 | +36 | V | ||
0P2V pin to GND pin | –0.4 | +36 | V | ||
0P4V pin to GND pin | –0.4 | +36 | V | ||
0P8V pin to GND pin | –0.4 | +36 | V | ||
1P6V pin to GND pin | –0.4 | +36 | V | ||
3P2V pin to GND pin | –0.4 | +36 | V | ||
6P4V1 pin to GND pin | –0.4 | +36 | V | ||
6P4V2 pin to GND pin | –0.4 | +36 | V | ||
Current | Peak output | Internally limited | |||
Temperature | Operating virtual junction, TJ | –40 | 125 | °C |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
Tstg | Storage temperature range | –65 | 150 | °C | ||
V(ESD) | Electrostatic discharge | TPS7A4700 | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | –1000 | 1000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | –500 | 500 | ||||
TPS7A4701 | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | –2500 | 2500 | V | ||
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | –500 | 500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VI | 3.0 | 35.0 | V | ||
VO | 1.4 | 34.0 | V | ||
VEN | 0 | VIN | V | ||
IO | 0 | 1.0 | A |
THERMAL METRIC(1) | TPS7A47xx | UNIT | |
---|---|---|---|
RGW | |||
20 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 32.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 27 | |
RθJB | Junction-to-board thermal resistance | 11.9 | |
ψJT | Junction-to-top characterization parameter | 0.3 | |
ψJB | Junction-to-board characterization parameter | 11.9 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.7 |