SBVS121E August   2010  – May 2015 TPS7A49

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Internal Current Limit
      2. 8.3.2 Programmable Soft-Start
      3. 8.3.3 Enable Pin Operation
      4. 8.3.4 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Dropout Operation
      3. 8.4.3 Disabled
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Adjustable Operation
      2. 9.1.2  Capacitor Recommendations
      3. 9.1.3  Input and Output Capacitor Requirements
      4. 9.1.4  Noise-Reduction and Feed-Forward Capacitor Requirements
      5. 9.1.5  Maximum AC Performance
      6. 9.1.6  Output Noise
      7. 9.1.7  Post DC-DC Converter Filtering
      8. 9.1.8  Power-Supply Rejection
      9. 9.1.9  Transient Response
      10. 9.1.10 Audio Applications
      11. 9.1.11 Power for Precision Analog
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don’ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 11.1.2 Power Dissipation
    2. 11.2 Layout Example
    3. 11.3 Package Mounting
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Evaluation Modules
        2. 12.1.1.2 Spice Models
      2. 12.1.2 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To help eliminate these problems, bypass the IN pin to ground with a low-ESR ceramic bypass capacitor with an X5R or X7R dielectric.

The GND pin must be tied directly to the PowerPAD under the device. Connect the PowerPAD to any internal PCB ground planes using multiple vias directly under the device.

Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized to maximize performance and ensure stability. Every capacitor (CIN, COUT, CNR/SS, and CFF) must be placed as close as possible to the device and on the same side of the PCB as the regulator itself.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because these circuits can negatively affect system performance, and can even cause instability.

11.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance

To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate ground planes for VIN and VOUT, with each ground plane star-connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to the GND pin of the device.

11.1.2 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (PD) can be approximated by the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 9:

Equation 9. TPS7A49 q_pd_bvs067.gif

Figure 36 shows the maximum ambient temperature versus the power dissipation of the TPS7A49. Figure 36 assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board thermal impedances vary widely. If the application requires high power dissipation, having a thorough understanding of the board temperature and thermal impedances is helpful to ensure the TPS7A49 does not operate above a junction temperature of 125°C.

TPS7A49 D001_SBVS121.gifFigure 36. Maximum Ambient Temperature vs Device Power Dissipation

Estimating the junction temperature can be done by using the thermal metrics ΨJT and ΨJB; see the Thermal Information table. These metrics are a more accurate representation of the heat transfer characteristics of the die and the package than RθJA. The junction temperature can be estimated with Equation 10.

Equation 10. TPS7A49 q_new_metrics_bvs066.gif

where

  • PD is the power dissipation given by Equation 9,
  • TT is the temperature at the center-top of the device package, and
  • TB is the PCB temperature measured 1 mm away from the device package on the PCB surface.

NOTE

Both TT and TB can be measured on actual application boards using a thermo‐gun (an infrared thermometer).

For more information about measuring TT and TB, see the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com.

11.2 Layout Example

TPS7A49 ai_pcb_bvs121.gif
NOTE: CIN and COUT are size 1206 capacitors and CNR, R1, and R2 are size 0402.
Figure 37. PCB Layout Example

11.3 Package Mounting

Solder pad footprint recommendations for the TPS7A49 are available at the end of this product data sheet and at www.ti.com.