SBVS121E August   2010  – May 2015 TPS7A49

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Internal Current Limit
      2. 8.3.2 Programmable Soft-Start
      3. 8.3.3 Enable Pin Operation
      4. 8.3.4 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Dropout Operation
      3. 8.4.3 Disabled
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Adjustable Operation
      2. 9.1.2  Capacitor Recommendations
      3. 9.1.3  Input and Output Capacitor Requirements
      4. 9.1.4  Noise-Reduction and Feed-Forward Capacitor Requirements
      5. 9.1.5  Maximum AC Performance
      6. 9.1.6  Output Noise
      7. 9.1.7  Post DC-DC Converter Filtering
      8. 9.1.8  Power-Supply Rejection
      9. 9.1.9  Transient Response
      10. 9.1.10 Audio Applications
      11. 9.1.11 Power for Precision Analog
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don’ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 11.1.2 Power Dissipation
    2. 11.2 Layout Example
    3. 11.3 Package Mounting
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Evaluation Modules
        2. 12.1.1.2 Spice Models
      2. 12.1.2 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage IN pin to GND pin –0.3 36 V
OUT pin to GND pin –0.3 33 V
OUT pin to IN pin –36 0.3 V
FB pin to GND pin –0.3 2 V
FB pin to IN pin –36 0.3 V
EN pin to IN pin –36 0.3 V
EN pin to GND pin –0.3 36 V
NR/SS pin to IN pin –36 0.3 V
NR/SS pin to GND pin –0.3 2 V
Current Peak output Internally limited
Temperature Operating virtual junction, TJ –40 125 °C
Storage, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input supply voltage 3 35 V
VEN Enable supply voltage 0 VIN V
VOUT Output voltage VFB 33 V
IOUT Output current 0 150 mA
TJ Operating junction temperature –40 125 °C
CIN Input capacitor 2.2 10 µF
COUT Output capacitor 2.2 10 µF
CNR Noise reduction capacitor 0 10 nF
CFF Feed-forward capacitor 0 10 nF
R2 Lower feedback resistor 237 kΩ

6.4 Thermal Information

THERMAL METRIC(1) TPS7A49 UNIT
DGN
(HVSSOP PowerPAD)		 DRB (VSON)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 63.4 47.7 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 53 55.3 °C/W
RθJB Junction-to-board thermal resistance 37.4 23.3 °C/W
ψJT Junction-to-top characterization parameter 3.7 1.1 °C/W
ψJB Junction-to-board characterization parameter 37.1 23.5 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 13.5 7.0 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

At TJ = –40°C to 125°C, VIN = VOUT(nom) + 1 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 μF, COUT = 2.2 μF, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 3 35 V
VREF Internal reference(4) TJ = 25°C, VNR/SS = VREF 1.176 1.188 1.212 V
VFB Feedback voltage 1.185 V
VOUT Output voltage range(1) VIN ≥ VOUT(nom) + 1 V VREF 33 V
Nominal accuracy TJ = 25°C, VIN = VOUT(nom) + 0.5 V –1.5 1.5 %VOUT
Overall accuracy VOUT(nom) + 1 V ≤ VIN ≤ 35 V,
1 mA ≤ IOUT ≤ 150 mA		 –2.5 2.5 %VOUT
TPS7A49 q_line_reg_bvs121.gif Line regulation TJ = 25°C, VOUT(nom) + 1 V ≤ VIN ≤ 35 V 0.086 %VOUT
TPS7A49 q_load_reg_bvs121.gif Load regulation TJ = 25°C, 1 mA ≤ IOUT ≤ 150 mA 0.04 %VOUT
VDO Dropout voltage VIN = 95% VOUT(nom), IOUT = 100 mA 260 mV
VIN = 95% VOUT(nom), IOUT = 150 mA 333 600 mV
ILIM Current limit VOUT = 90% VOUT(nom) 220 309 500 mA
IGND Ground current IOUT = 0 mA 49 100 μA
IOUT = 100 mA 800 μA
ISHDN Shutdown supply current VEN = 0.4 V 0.8 3 μA
IFB Feedback current(2) 3 100 nA
IEN Enable current VEN = VIN = VOUT(nom) + 1 V 0.02 1 μA
VEN = VIN = 35 V 0.2 1 μA
VEN(high) Enable high-level voltage 2.1 VIN V
VEN(low) Enable low-level voltage 0 0.4 V
Vn Output noise voltage VIN = 3 V, VOUT(nom) = VREF, COUT = 10 μF, CNR/SS = 10 nF, BW = 10 Hz to 100 kHz 15.4 μVRMS
VIN = 6.2 V, VOUT(nom) = 5 V, COUT = 10 μF, CNR/SS = CFF(3) = 10 nF, BW = 10 Hz to
100 kHz		 21.15 μVRMS
PSRR Power-supply rejection ratio VIN = 6.2 V, VOUT(nom) = 5 V, COUT = 10 μF, CNR/SS = CFF(3) = 10 nF, f = 120 Hz 72 dB
Tsd Thermal shutdown temperature Shutdown, temperature increasing 170 °C
Reset, temperature decreasing 150 °C
TJ Operating junction temperature –40 125 °C
(1) To ensure stability at no load conditions, a current from the feedback resistive network equal to or greater than 5 μA is required.
(2) IFB > 0 flows out of the device.
(3) CFF refers to a feed-forward capacitor connected to the FB and OUT pins.
(4) VREF is measured at the NR/SS pin.

6.6 Typical Characteristics

At TJ = –40°C to 125°C, VIN = VOUT(nom) + 1 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 μF, COUT = 2.2 μF, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted. Typical values are at TA = 25°C.
TPS7A49 tc_vfb-vin_bvs121.gif
Figure 1. Feedback Voltage vs Input Voltage
TPS7A49 tc_ignd-vin_25c_bvs121.gif
Figure 3. Ground Current vs Input Voltage
TPS7A49 tc_ignd-iout_bvs121.gif
Figure 5. Ground Current vs Output Current
TPS7A49 tc_iq-vin_bvs121.gif
Figure 7. Quiescent Current vs Input Voltage
TPS7A49 tc_vdo-iout_bvs121.gif
Figure 9. Dropout Voltage vs Output Current
TPS7A49 tc_ilim-vin_bvs121.gif
Figure 11. Current Limit vs Input Voltage
TPS7A49 tc_ven-tmp_bvs121.gif
Figure 13. Enable Threshold Voltage vs Temperature
TPS7A49 tc_line_reg_bvs121.gif
Figure 15. Line Regulation
TPS7A49 tc_load_reg_bvs121.gif
Figure 17. Load Regulation
TPS7A49 tc_soft-start_0nf_bvs121.gif
Figure 19. Capacitor-Programmable Soft-Start
TPS7A49 tc_line_trans_18v_bvs121.gif
Figure 21. Line Transient Response
TPS7A49 tc_load_trans_1ma_bvs121.gif
Figure 23. Load Transient Response
TPS7A49 tc_ifb-tmp_bvs121.gif
Figure 2. Feedback Current vs Temperature
TPS7A49 tc_ignd-vin_100ma_bvs121.gif
Figure 4. Ground Current vs Input Voltage
TPS7A49 tc_ien-ven_bvs121.gif
Figure 6. Enable Current vs Enable Voltage
TPS7A49 tc_ishdn-vin_bvs121.gif
Figure 8. Shutdown Current vs Input Voltage
TPS7A49 tc_vdo-tmp_bvs121.gif
Figure 10. Dropout Voltage vs Temperature
TPS7A49 tc_ilim-tmp_bvs121.gif
Figure 12. Current Limit vs Temperature
TPS7A49 tc_psrr-cout_bvs121.gif
Figure 14. Power-Supply Rejection Ratio vs COUT
TPS7A49 tc_psrr-cnr_bvs121.gif
Figure 16. Power-Supply Rejection Ratio vs CNR/SS
TPS7A49 tc_psrr-cbyp_bvs121.gif
Figure 18. Power-Supply Rejection Ratio vs CFF
TPS7A49 tc_soft-start_10nf_bvs121.gif
Figure 20. Capacitor-Programmable Soft-Start
TPS7A49 tc_line_trans_33v_bvs121.gif
Figure 22. Line Transient Response
TPS7A49 tc_load_trans_120ma_bvs121.gif
Figure 24. Load Transient Response