SBVS295A November   2019  – March 2020 TPS7A52

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Powering RF Components
      2.      Powering Digital Loads
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation Features
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 System Start-Up Features
        1. 7.3.2.1 Programmable Soft Start (NR/SS Pin)
        2. 7.3.2.2 Internal Sequencing
          1. 7.3.2.2.1 Enable (EN)
          2. 7.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 7.3.2.2.3 Active Discharge
        3. 7.3.2.3 Power-Good Output (PG)
      3. 7.3.3 Internal Protection Features
        1. 7.3.3.1 Foldback Current Limit (ICL)
        2. 7.3.3.2 Thermal Protection (Tsd)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
      3. 7.4.3 Current Limit Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Recommended Capacitor Types
        1. 8.1.1.1 Input and Output Capacitor Requirements (CIN and COUT)
        2. 8.1.1.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
        3. 8.1.1.3 Feed-Forward Capacitor (CFF)
      2. 8.1.2  Soft Start and Inrush Current
      3. 8.1.3  Optimizing Noise and PSRR
      4. 8.1.4  Charge Pump Noise
      5. 8.1.5  Current Sharing
      6. 8.1.6  Adjustable Operation
      7. 8.1.7  Power-Good Operation
      8. 8.1.8  Undervoltage Lockout (UVLO) Operation
      9. 8.1.9  Dropout Voltage (VDO)
      10. 8.1.10 Device Behavior During Transition From Dropout Into Regulation
      11. 8.1.11 Load Transient Response
      12. 8.1.12 Reverse Current Protection Considerations
      13. 8.1.13 Power Dissipation (PD)
      14. 8.1.14 Estimating Junction Temperature
      15. 8.1.15 TPS7A52EVM Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Typical Characteristics

at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT = 47 µF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
TPS7A52 D008-SBVS295-03.gif
VIN = 1.2 V, VBIAS = 5 V,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF
Figure 1. PSRR vs Frequency and IOUT
TPS7A52 D038-SBVS311-04.gif
IOUT = 1 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF
Figure 3. PSRR vs Frequency and VIN
TPS7A52 Noise_vs_Vin.gif
IOUT = 1 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 5. Output Voltage Noise vs Frequency and VIN
TPS7A52 D010-SBVS295-07.gif
IOUT = 4 A, VBIAS = 0 V
Figure 7. Dropout Voltage vs Input Voltage Without Bias
TPS7A52 D001-SBVS295-04.gif
VIN = 1.4 V, VBIAS = 0 V
Figure 9. Dropout Voltage vs Output Current Without Bias
TPS7A52 D002-SBVS295-05.gif
VIN = 5.5 V
Figure 11. Dropout Voltage vs Output Current (High VIN)
TPS7A52 D005-SBVS295-01.gif
VOUT = 0.8 V, VBIAS = 0 V, IOUT = 5 mA
Figure 13. Line Regulation Without Bias
TPS7A52 D015-SBVS311-02.gif
VIN = 1.1 V, IOUT = 5 mA
Figure 15. Quiescent Current vs Bias Voltage
TPS7A52 D017-SBVS311-05.gif
VIN = 1.1 V
Figure 17. Shutdown Current vs Bias Voltage
TPS7A52 D019-SBVS311-03.gif
Figure 19. VIN UVLO vs Temperature
TPS7A52 D026-SBVS311-01.gif
VIN = 1.4 V, 6.5 V
Figure 21. Enable Threshold vs Temperature
TPS7A52 D029-SBVS311-02.gif
VIN = 6.5 V
Figure 23. PG Voltage vs PG Current Sink
TPS7A52 D011-SBVS295-02.gif
VIN = 1.1 V, VBIAS = 3 V
Figure 25. Foldback Current Limit vs Temperature
TPS7A52 D037-SBVS311-03.gif
VIN = 1.4 V, IOUT = 1 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF
Figure 2. PSRR vs Frequency and VBIAS
TPS7A52 D009-SBVS295-04.gif
VIN = VOUT + 0.6 V,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF
Figure 4. PSRR vs Frequency and IOUT for VOUT = 5 V
TPS7A52 Load_trans_vs_Vout_no_bias.gif
IOUT, DC = 100 mA, COUT = 47 µF || 10 µF || 10 µF,
CNR/SS = CFF = 10 nF, slew rate = 1 A/µs
Figure 6. Load Transient vs Time and VOUT Without Bias
TPS7A52 D012-SBVS295-02.gif
IOUT = 4 A, VBIAS = 6.5 V
Figure 8. Dropout Voltage vs Input Voltage With Bias
TPS7A52 D007-SBVS295-02.gif
VIN = 1.1 V, VBIAS = 3 V
Figure 10. Dropout Voltage vs Output Current With Bias
TPS7A52 D006-SBVS295-02.gif
VIN = 1.4 V, VBIAS = 0 V
Figure 12. Load Regulation With Bias
TPS7A52 D011-SBVS311-01.gif
VBIAS = 0 V, IOUT = 5 mA
Figure 14. Quiescent Current vs Input Voltage
TPS7A52 D016-SBVS311-04.gif
VBIAS = 0 V
Figure 16. Shutdown Current vs Input Voltage
TPS7A52 D018-SBVS311-06.gif
VBIAS = 0 V
Figure 18. NR/SS Current vs VIN and Temperature
TPS7A52 D020-SBVS311-04.gif
VIN = 1.1 V
Figure 20. VBIAS UVLO vs Temperature
TPS7A52 D028-SBVS311-01.gif
Figure 22. PG Voltage vs PG Current Sink
TPS7A52 D039-SBVS311-01.gif
Figure 24. PG Threshold vs Temperature