Refer to the PDF data sheet for device specific package drawings
The TPS7A53-Q1 device is a low-noise (4.4 µVRMS), low-dropout linear regulator (LDO) capable of sourcing 3 A with only 180 mV of maximum dropout. The device output voltage is adjustable from 0.8 V to 5.15 V using an external resistor divider.
The combination of low-noise (4.4 µVRMS), high-PSRR, and high output current capability makes the TPS7A53-Q1 an excellent choice to power noise-sensitive components, such as those found in radar power and infotainment applications. The high performance of this device limits power-supply-generated phase noise and clock jitter, making this device an excellent choice for powering RF amplifiers, radar sensors, and chipsets. Specifically, RF amplifiers benefit from the high-performance and 5.0-V output capability of the device.
For digital loads such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs) that require low-input, low-output (LILO) voltage operation, the exceptional accuracy (1% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A53-Q1 provide optimal system performance.
The versatility of the TPS7A53-Q1 makes the device a component of choice for many demanding applications.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS7A53-Q1 | VQFN (20) | 3.50 mm × 3.50 mm |
VQFNP (20)
with wettable flank |
4.00 mm x 4.00 mm |
PIN | DESCRIPTION | ||
---|---|---|---|
NAME | NO. | I/O | |
BIAS | 12 | I | BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions (that is, VIN = 1.2 V, VOUT = 1 V) to reduce power dissipation across the die. The use of a BIAS voltage improves dc and ac performance for VIN ≤ 2.2 V. A 10-µF capacitor or larger must be connected between this pin and ground. If not used, this pin must be left floating or tied to ground. |
DNC | 5 | Do not connect. Leave this pin floating or connect this pin to ground. | |
EN | 14 | I | Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable functionality is not required, this pin must be connected to IN or BIAS. |
FB | 3 | I | Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FB to OUT (as close to the device as possible) is recommended to maximize ac performance. The use of a feed-forward capacitor can disrupt PG (power good) functionality. |
GND | 8, 18 | — | Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection. |
IN | 15-17 | I | Input supply voltage pin. A 10-µF or larger ceramic capacitor (5 µF or greater of capacitance) from IN to ground is recommended to reduce the impedance of the input supply. Place the input capacitor as close to the input as possible. |
NC | 2, 6, 7, 9, 10, 11 | No internal connection | |
NR/SS | 13 | — | Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference voltage noise and also enables the soft-start function. Although not required, a 10-nF or larger capacitor is recommended to be connected from NR/SS to GND (as close to the pin as possible) to maximize ac performance. |
OUT | 1, 19, 20 | O | Regulated output pin. A 47-µF or larger ceramic capacitor (25 µF or greater of capacitance) from OUT to ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the OUT pin to the load. |
PG | 4 | O | Active-high, power-good pin. An open-drain output indicates when the output voltage reaches VIT(PG) of the target. The use of a feed-forward capacitor may disrupt PG (power good) functionality. |
Thermal pad | — | Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | IN, BIAS, PG, EN | –0.3 | 7.0 | V |
OUT | –0.3 | VIN + 0.3(2) | ||
NR/SS, FB | –0.3 | 3.6 | ||
Current | OUT | Internally limited | A | |
PG (sink current into device) | 5 | mA | ||
Operating junction temperature, TJ | –55 | 150 | °C | |
Storage temperature, Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002((1) | ±2000 | V |
Charged-device model (CDM), per AEC Q100-011 | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Input supply voltage range(1) | 1.1 | 6.5 | V | |
VBIAS | Bias supply voltage range(1) | 3.0 | 6.5 | V | |
VEN | Enable voltage range | 0 | 6.5 | V | |
IOUT | Output current | 0 | 3 | A | |
CIN | Input capacitor | 10 | 47 | µF | |
COUT | Output capacitor(2) | 47 | 47 || 10 || 10 | µF | |
CBIAS | Bias capacitor (3) | 10 | µF | ||
RPG | Power-good pullup resistance | 10 | 100 | kΩ | |
CNR/SS | NR/SS capacitor | 10 | nF | ||
CFF | Feed-forward capacitor | 10 | nF | ||
R1 | Top resistor value in feedback network for adjustable operation(4) | 12.1 | kΩ | ||
R2 | Bottom resistor value in feedback network for adjustable operation(5) | 160 | kΩ | ||
TJ | Operating junction temperature | –40 | 150 | °C |