SBVS412A November   2022  – December 2022 TPS7A53A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Shutdown
      2. 7.3.2 Active Discharge
      3. 7.3.3 Power-Good Output (PG)
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input, Output, and Bias Capacitor Requirements
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Output Noise
      4. 8.1.4 Estimating Junction Temperature
      5. 8.1.5 Soft Start, Sequencing, and Inrush Current
      6. 8.1.6 Power-Good Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Board Layout
        2. 8.4.1.2 RTJ Package — High CTE Mold Compound
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RTJ|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Typical Characteristics

at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.3 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT = 47 µF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)

GUID-20221031-SS0I-C2PN-PF09-2K0DPDWSDR2Z-low.png
VIN = 1.3 V, VBIAS = 5 V, VOUT = 1.0 V, COUT = 10 µF,
CBIAS = 0.1 μF, CSS = 10 nF
Figure 6-1 PSRR vs Frequency and IOUT
GUID-20221031-SS0I-NLT1-TBPL-21BHKWM68RNG-low.png
IOUT = 2 A, VBIAS = 5 V, VOUT = 1.0 V, COUT = 10 µF,
CBIAS = 0.1 μF, CSS = 10 nF
Figure 6-3 PSRR vs Frequency and VIN for IOUT = 2 A
GUID-20221031-SS0I-90JN-MWJC-TVDNJDWBDBW7-low.png
IOUT = 3 A, VBIAS = 5 V, VOUT = 1.0 V, CBIAS = 0.1 μF,
CSS = 10 nF
Figure 6-5 PSRR vs Frequency and COUT
GUID-20221031-SS0I-Z8CH-S9NX-GW9NL9KFWGTR-low.png
VIN = VEN = 1.3 V, VBIAS = 5 V, VOUT = 1.0 V, CIN = 10 μF, COUT = 10 μF, CSS = 10 nF
Figure 6-7 BIAS PSRR vs Frequency and IOUT
GUID-20221031-SS0I-WFP9-FD52-SP377ZXQ8MMH-low.png
VIN = 1.3 V, VOUT = 1.0 V, VBIAS = 5 V, COUT = 10 µF, CSS = 10 nF, CBIAS = 0.1 μF, RMS noise BW = 10 Hz to 100 kHz
Figure 6-9 Spectral Noise Density vs Frequency and IOUT
GUID-20221031-SS0I-QQ8Q-FDFT-TKXKSRTCCMXW-low.png
VIN = 1.3 V, VOUT = 1.0 V, VBIAS = 5 V, CSS = 10 nF,
CBIAS = 0.1 μF, RMS noise BW = 10 Hz to 100 kHz
Figure 6-11 Spectral Noise Density vs Frequency and COUT
GUID-20221207-SS0I-TP0V-MVSH-M8NZ0TJ9R82T-low.png
VIN = 1.3 V, VOUT = 1.0 V, VBIAS = 5.0 V, IOUT = 3 A,
COUT = 10 µF, CSS = 1 nF
Figure 6-13 Start-Up Waveform for CSS = 1 nF
GUID-20221207-SS0I-QK17-Z12L-RPBDXWS3TZ9W-low.png
VIN = 1.3 V, VOUT = 1.0 V, VBIAS = 5.0 V, IOUT = 3 A,
COUT = 10 µF, CSS = 22 nF
Figure 6-15 Start-Up Waveform for CSS = 22 nF
GUID-20221207-SS0I-1ZL0-RC17-D4PCHPKSF6SC-low.png
IOUT, DC = 1.5 A, COUT = 10 µF,
CSS = CFF = 10 nF, slew rate = 1 A/µs
Figure 6-17 Line Transient for VOUT With Bias
GUID-20221019-SS0I-T8NW-2VL3-NRC9THGZJ8VW-low.png
VBIAS = 5 V, VOUT = 1.0 V
Figure 6-19 IN-to-OUT Dropout Voltage vs Output Current
GUID-20221019-SS0I-S0H2-FMC6-5HPM3VKLMVGK-low.png
VIN = 1.25 V, VBIAS = 5 V, VOUT = 1.0 V
Figure 6-21 Load Regulation vs 0-mA to 50-mA Output Current
GUID-20221019-SS0I-QSLZ-GHKF-4NCD21VSPCSF-low.png
VOUT = 1.0 V, VBIAS = 5 V, IOUT = 50 mA
Figure 6-23 Line Regulation vs Input Voltage
GUID-20221019-SS0I-8TBR-NCQD-GTC03N2ZNMLB-low.png
VOUT = 1.0 V, VBIAS = 5.0 V, IOUT = 50 mA
Figure 6-25 IN Pin Quiescent Current vs
Input Voltage
GUID-20221019-SS0I-3M93-0CXX-70FZ3P4CRLH1-low.png
VOUT = 1.0 V, VBIAS = 5.0 V, IOUT = 3 A
Figure 6-27 BIAS Pin Quiescent Current vs
Input Voltage
GUID-20221019-SS0I-5DX8-LKSW-RWWF70ZWXSPF-low.png
VBIAS = 5 V, VEN = 0 V
Figure 6-29 Shutdown Current (GND Pin) vs
Input Voltage
GUID-20221019-SS0I-FRSG-RWBQ-WCVD6B1WZRVM-low.png
Temperature limited because of power dissipation
Figure 6-31 Current Limit vs Output Voltage
GUID-20221031-SS0I-3JSD-HBHR-ZSN7HVZCZ4ZG-low.png
IOUT = 1 A, VBIAS = 5 V, VOUT = 1.0 V, COUT = 10 µF,
CBIAS = 0.1 μF, CSS = 10 nF
Figure 6-2 PSRR vs Frequency and VIN for IOUT = 1 A
GUID-20221031-SS0I-RDFR-3F6C-KLPZSBNPQCLS-low.png
IOUT = 3 A, VBIAS = 5 V, VOUT = 1.0 V, COUT = 10 µF,
CBIAS = 0.1 μF, CSS = 10 nF
Figure 6-4 PSRR vs Frequency and VIN for IOUT = 3 A
GUID-20221031-SS0I-DTMQ-X7ZN-CL8S59W7MVW0-low.png
IOUT = 3 A, VBIAS = 5 V, VOUT = 1.0 V, CBIAS = 0.1 μF,
COUT = 10 μF
Figure 6-6 PSRR vs Frequency and CSS
GUID-20221031-SS0I-ZFHH-TBMN-XPK1GQXRP90S-low.png
VIN = VEN = 1.3 V, VOUT = 1.0 V, CIN = 10 μF, COUT = 10 μF, CSS = 10 nF
Figure 6-8 BIAS PSRR vs Frequency and VBIAS
GUID-20221031-SS0I-PQPC-8H8H-2Z4QHCLPDNX3-low.png
VIN = 1.3 V, VOUT = 1.0 V, COUT = 10 µF, CSS = 10 nF,
CBIAS = 0.1 μF, RMS noise BW = 10 Hz to 100 kHz
Figure 6-10 Spectral Noise Density vs Frequency and VBIAS
GUID-20221031-SS0I-QSML-F2SC-GW5STSH1NSJH-low.png
VIN = 1.3 V, VOUT = 1.0 V, VBIAS = 5 V, COUT = 10 μF,
CBIAS = 0.1 μF, RMS noise BW = 10 Hz to 100 kHz
Figure 6-12 Spectral Noise Density vs Frequency and CSS
GUID-20221207-SS0I-MDWV-MV6W-5LZ84H9H3NM5-low.png
VIN = 1.3 V, VOUT = 1.0 V, VBIAS = 5.0 V, IOUT = 3 A,
COUT = 10 µF, CSS = 10 nF
Figure 6-14 Start-Up Waveform vs Time for CSS = 10 nF
GUID-20221207-SS0I-S7MK-MTMT-LHGFXTD2KMGQ-low.png
VIN = VOUT + 0.3 V, VBIAS = VEN = 5 V, IOUT, DC = 10 mA,
slew rate = 1 A/µs, CSS = 10 nF, COUT = 10 µF
Figure 6-16 Load Transient for VOUT With Bias
GUID-20221207-SS0I-PVDT-H9PG-VXS28BSCC564-low.png
VBIAS = 5 V, IOUT = 3 A, COUT = 10 µF, CSS = 10 nF
 
Figure 6-18 Input Ramp Response
GUID-20221019-SS0I-DXL8-F5ZC-XSCPJSZ9NZRR-low.png
VIN = 1.25 V, VOUT = 1 V
Figure 6-20 BIAS-to-OUT Dropout Voltage vs Output Current
GUID-20221019-SS0I-JM41-55L4-M8QKZG3FHTLH-low.png
VIN = 1.25 V, VOUT = 1.0 V, VBIAS = 5 V
Figure 6-22 Load Regulation vs ≥50-mA Output Current
GUID-20221019-SS0I-WXXD-JKGF-TGJ86JGMKQK1-low.png
VIN = 5 V, VOUT = 1.0 V, IOUT = 50 mA
Figure 6-24 Output Voltage vs Bias Voltage
GUID-20221019-SS0I-L8GT-MCS0-MZTLJKDHV9W6-low.png
VOUT = 1.0 V, VBIAS = 5.0 V
Figure 6-26 IN Pin Quiescent Current vs
Output Current
GUID-20221019-SS0I-CBC7-4BBM-KNV8CG7KDF2S-low.png
VIN = 1.25 V, VBIAS = 5.0 V, VOUT = 1.0 V
Figure 6-28 BIAS Pin Quiescent Current vs
Output Current
GUID-20221019-SS0I-PFH8-PR0L-DLDLRJS7W5SB-low.png
VIN = 1.25 V, VEN = 0 V
Figure 6-30 Shutdown Current (GND Pin) vs
Bias Voltage