SBVS412A November   2022  – December 2022 TPS7A53A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Shutdown
      2. 7.3.2 Active Discharge
      3. 7.3.3 Power-Good Output (PG)
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input, Output, and Bias Capacitor Requirements
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Output Noise
      4. 8.1.4 Estimating Junction Temperature
      5. 8.1.5 Soft Start, Sequencing, and Inrush Current
      6. 8.1.6 Power-Good Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Board Layout
        2. 8.4.1.2 RTJ Package — High CTE Mold Compound
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RTJ|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5.0 V (5), and TJ = –40°C to 150°C (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF Internal reference Fixed 1 V only 1.0 V
VNR/SS NR/SS pin voltage Fixed 1 V only (4) 1 V
VBIAS(UVLO) Rising bias supply UVLO 1.4 1.8 V
VBIAS(UVLO),HYST Bias supply UVLO hysteresis 25 50 75 mV
ΔVOUT(ΔVIN) Accuracy (1)(6) VOUT + 2.5 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 3 A, -40°C ≤ TJ ≤ 125°C –1 ±0.5 1 %
VOUT + 2.5 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 3 A –1.3 ±0.5 1.3
ΔVOUT(ΔIOUT) Line regulation VOUT(nom) + 0.3 V ≤ VIN ≤ 6.0 V 0.025 %/V
VOUT Load regulation 50 mA ≤ IOUT ≤ 3 A 0.025 %/A
VDO(IN) VIN dropout voltage(2) IOUT = 3 A, VBIAS – VOUT(nom) ≥ 3.25 V(3), -40°C ≤ TJ ≤ 125°C 130 275 mV
IOUT = 3 A, VBIAS – VOUT(nom) ≥ 3.25 V(3) 130 285
VDO(BIAS) VBIAS dropout voltage(2) IOUT = 3 A, VIN = VBIAS 1.4 1.9 V
ICL (Fixed VOUT) Fixed VOUT, output current limit VOUT = 80% × VOUT(nom) 4.0 4.7 5.5 A
IBIAS BIAS pin current IOUT = 50 mA 0.7 1.2 mA
ISHDN Shutdown supply current (IGND) VEN ≤ 0.4 V, VIN = 1.25 V, VBIAS = 6 V 1 25 µA
IFB/SNS Feedback/sense pin current –0.3 0.12 0.3 µA
PSRR Power-supply rejection (VIN to VOUT) 1 kHz, IOUT = 2 A, VIN = 1.25 V, VOUT = 1.0 V 70 dB
3 MHz, IOUT = 2 A, VIN = 1.25 V, VOUT = 1.0 V 27 dB
Power-supply rejection (VBIAS to VOUT) 1 kHz, IOUT = 2 A, VIN = 1.25 V, VOUT = 1.0 V 65 dB
3 MHz, IOUT = 2 A, VIN = 1.25 V, VOUT = 1.0 V 28 dB
Vn Output noise voltage BW = 10 Hz to 100 kHz, IOUT = 2 A, CSS = 1 nF 7 μVrms
tSTR Minimum startup time CSS = 10 nF, VOUT = 1.0 V 2 ms
ISS Soft-start charging current tSS = 4.8 x VOUT(NOM) / 0.8 V, VOUT = 1.0 V 6 µA
VEN(hi) Enable input high level 1.1 5.5 V
VEN(lo) Enable input low level 0 0.4 V
VEN(hys) Enable pin hysteresis 70 mV
VEN(dg) Enable pin deglitch time 15 µs
IEN Enable pin current VEN = 5 V 0.1 0.25 µA
VIT PG trip threshold VOUT decreasing 85 90 94 %VOUT
VHYS PG trip hysteresis 2.5 %VOUT
VPG(lo) PG output low voltage IPG = 1 mA (sinking), VOUT < VIT 0.3 V
IPG(lkg) PG leakage current VPG = 5.25 V, VOUT > VIT 0.001 0.05 µA
RPULLDOWN Output Pulldown resistor VBIAS = 5 V, VEN = 0 V 0.5 kΩ
TSD Thermal shutdown temperature Shutdown, temperature increasing 165 ℃
Reset, temperature decreasing 140
(1) Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
(3) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 6.
(4) For fixed voltage, NR/SS voltage is equal to output voltage.
(5) VBIAS = VDO_MAX(BIAS) + VOUT for VOUT ≥ 3.1V.
(6) The device is not tested under conditions where VIN > VOUT + 0.85 V and IOUT = 3 A, because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.