SBVS446A August   2023  – January 2024 TPS7A53B

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Voltage Regulation Features
        1. 6.3.1.1 DC Regulation
        2. 6.3.1.2 AC and Transient Response
      2. 6.3.2 System Start-Up Features
        1. 6.3.2.1 Programmable Soft-Start (NR/SS Pin)
        2. 6.3.2.2 Internal Sequencing
          1. 6.3.2.2.1 Enable (EN)
          2. 6.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 6.3.2.2.3 Active Discharge
        3. 6.3.2.3 Power-Good Output (PG)
      3. 6.3.3 Internal Protection Features
        1. 6.3.3.1 Foldback Current Limit (ICL)
        2. 6.3.3.2 Thermal Protection (Tsd)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Regulation
      2. 6.4.2 Disabled
      3. 6.4.3 Current Limit Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Recommended Capacitor Types
        1. 7.1.1.1 Input and Output Capacitor Requirements (CIN and COUT)
        2. 7.1.1.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
        3. 7.1.1.3 Feed-Forward Capacitor (CFF)
      2. 7.1.2  Soft-Start and Inrush Current
      3. 7.1.3  Optimizing Noise and PSRR
      4. 7.1.4  Charge Pump Noise
      5. 7.1.5  Current Sharing
      6. 7.1.6  Adjustable Operation
      7. 7.1.7  Power-Good Operation
      8. 7.1.8  Undervoltage Lockout (UVLO) Operation
      9. 7.1.9  Dropout Voltage (VDO)
      10. 7.1.10 Device Behavior During Transition From Dropout Into Regulation
      11. 7.1.11 Load Transient Response
      12. 7.1.12 Reverse Current Protection Considerations
      13. 7.1.13 Power Dissipation (PD)
      14. 7.1.14 Estimating Junction Temperature
      15. 7.1.15 TPS7A53EVM Thermal Analysis
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.5 V (whichever is greater), VBIAS = open, VOUT(nom) = 0.5 V,  IOUT = 10 mA, VEN = 1.1 V, CIN = 10 µF, COUT = 47 µF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VFB Feedback voltage 0.5 V
VNR/SS NR/SS pin voltage 0.5 V
VUVLO+(IN) Rising input supply UVLO with BIAS VIN rising with VBIAS = 3V 1.02 1.085 V
VUVLO-(IN) Falling input supply UVLO with BIAS VIN falling with VBIAS = 3V 0.55 0.7 V
VUVLO+(IN) Rising input supply UVLO without BIAS VIN rising 1.31 1.39 V
VUVLO-(IN) Falling input supply UVLO without BIAS VIN falling 0.65 1.057 V
VUVLO+(BIAS) Rising bias supply UVLO VBIAS rising, VIN = 1.1V 2.83 2.9 V
VUVLO-(BIAS) Falling bias supply UVLO VBIAS falling, VIN = 1.1V 2.45 2.54 V
VOUT Output voltage range 0.5 5.15 V
Output voltage accuracy 1.4 V ≤ VIN ≤ 6.5 V,
0.5V ≤ VOUT ≤ 5.15V,
5mA ≤ IOUT ≤ 3A		 -0.75 0.75 %
VIN =1.1V,
5mA ≤ IOUT ≤ 3A,
3V ≤ VBIAS ≤ 6.5V		 -0.5 0.5
ΔVOUT/ΔVIN Line regulation IOUT = 5mA,
1.4V ≤ VIN ≤ 6.5V		 0.03 mV/V
ΔVOUT/ΔIOUT Load regulation 5mA ≤ IOUT ≤ 3A
3V ≤ VBIAS ≤ 6.5V
VIN = 1.1V		 0.07 mV/A
5mA ≤ IOUT ≤ 3A 0.012 mV/A
VOS Error amplifier offset voltage VIN = 1.4V, IOUT = 5mA -2.5 2.5 mV
VDO Dropout voltage VIN = 1.4V, IOUT = 3A,
VFB = 0.5V – 3%		 105 175 mV
VIN = 5.4V, IOUT = 3A,
VFB = 0.5V – 3%		 170 280
VIN = 5.6V, IOUT = 3A,
VFB = 0.5V – 3%		 215 375
VIN = 1.1V,
3.0V ≤ VBIAS ≤ 6.5V,
IOUT = 3A, VFB = 0.5V – 3%		 60 110
ILIM Output current limit VOUT forced at 0.9 × VOUT(nom),
VOUT(nom) = 5.0V		 3.6 4.2 4.9 A
ISC Short-circuit current limit RLOAD = 20mΩ 2
IGND GND pin current VIN = 6.5V, IOUT = 5mA 3 4.3 mA
VIN = 1.4 V, IOUT = 3 A 4.3 5.5
Shutdown, PG = open,
VIN = 6.5V, VEN = 0.5V		 25 µA
IEN EN pin current VIN = 6.5V,
VEN = 0V and 6.5V		 0.5 µA
IBIAS BIAS pin current VIN = 1.1V, VBIAS = 6.5V,
VOUT(nom) = 0.5V, IOUT = 3A		 2.3 3.5 mA
VIL(EN) EN pin low-level input voltage (disable device) 0 0.5 V
VIH(EN) EN pin high-level input voltage (enable device) 1.1 6.5 V
VIT-(PG) Falling PG pin threshold For falling VOUT 80% × VOUT 86% × VOUT 91% × VOUT V
VIT+(PG) Rising PG pin threshold For rising VOUT 85% × VOUT 91% × VOUT 96% × VOUT V
VOL(PG) PG pin low-level output voltage VOUT < VIT(PG),
IPG = –1mA (current into device)		 0.4 V
Ilkg(PG) PG pin leakage current VOUT > VIT(PG), VPG = 6.5V 1 µA
INR/SS NR/SS pin charging current VNR/SS = GND, VIN = 6.5V 4 6.2 9 µA
IFB FB pin leakage current VIN = 6.5V 100 nA
RNR NR resistor value 250 kΩ
PSRR Power-supply rejection ratio VIN = 1.1V, VOUT = 0.5V,
VBIAS = 5V, IOUT = 3A,
CNR/SS = 10nF, CFF = 10nF,
COUT = 47µF || 10µF || 10µF,
f = 10kHz		 53 dB
VIN = 1.1V, VOUT = 0.5V,
VBIAS = 5V, IOUT = 3A,
CNR/SS = 10nF, CFF = 10nF,
COUT = 47µF || 10µF || 10µF,
f = 500kHz		 48
Vn Output noise voltage Bandwidth = 10Hz to 100kHz,
VIN = 1.1V, VOUT = 0.5V,
VBIAS = 5V, IOUT = 3A,
CNR/SS = 10nF, CFF = 10nF,
COUT = 47µF || 10µF || 10µF		 4.6 µVRMS
Bandwidth = 10Hz to 100kHz,
VOUT = 5V, IOUT = 3A,
CNR/SS = 10nF, CFF = 10nF,
COUT = 47µF || 10µF || 10µF		 13.9
Tsd+ Thermal shutdown temperature increasing Shutdown, temperature increasing 160 °C
Tsd- Thermal shutdown temperature decreasing Reset, temperature decreasing 140