SBVS311A November   2019  – March 2020 TPS7A54

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Powering Digital Loads
  3. 3 Description
    1.     Powering RF Components
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation Features
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 System Start-Up Features
        1. 7.3.2.1 Programmable Soft Start (NR/SS Pin)
        2. 7.3.2.2 Internal Sequencing
          1. 7.3.2.2.1 Enable (EN)
          2. 7.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 7.3.2.2.3 Active Discharge
        3. 7.3.2.3 Power-Good Output (PG)
      3. 7.3.3 Internal Protection Features
        1. 7.3.3.1 Foldback Current Limit (ICL)
        2. 7.3.3.2 Thermal Protection (Tsd)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
      3. 7.4.3 Current Limit Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Recommended Capacitor Types
        1. 8.1.1.1 Input and Output Capacitor Requirements (CIN and COUT)
        2. 8.1.1.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
        3. 8.1.1.3 Feed-Forward Capacitor (CFF)
      2. 8.1.2  Soft Start and Inrush Current
      3. 8.1.3  Optimizing Noise and PSRR
      4. 8.1.4  Charge Pump Noise
      5. 8.1.5  Current Sharing
      6. 8.1.6  Adjustable Operation
      7. 8.1.7  Power-Good Operation
      8. 8.1.8  Undervoltage Lockout (UVLO) Operation
      9. 8.1.9  Dropout Voltage (VDO)
      10. 8.1.10 Device Behavior During Transition From Dropout Into Regulation
      11. 8.1.11 Load Transient Response
      12. 8.1.12 Reverse Current Protection Considerations
      13. 8.1.13 Power Dissipation (PD)
      14. 8.1.14 Estimating Junction Temperature
      15. 8.1.15 TPS7A54EVM Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2.2 Internal Sequencing

Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because of the high power levels inherent in a PDN, and the variations between all of the supplies. As shown in Figure 42 and Table 2, the LDO turnon and turnoff time is set by the enable circuit (EN) and undervoltage lockout circuits (UVLO1,2(IN) and UVLOBIAS).

TPS7A54 ai_en_circuit_sbvs291.gifFigure 42. Simplified Turnon Control

Table 2. Internal Sequencing Functionality Table

INPUT VOLTAGE BIAS VOLTAGE ENABLE STATUS LDO STATUS ACTIVE DISCHARGE POWER GOOD
VIN ≥ VUVLO_1,2(IN) VBIAS ≥ VUVLO(BIAS) EN = 1 On Off PG = 1 when VOUT ≥ VIT(PG)
EN = 0 Off On PG = 0
VBIAS < VUVLO(BIAS) + VHYS(BIAS) EN = don't care Off On(1)
VIN < VUVLO_1,2(IN) – VHYS1,2(IN) BIAS = don't care Off
IN = don't care VBIAS ≥ VUVLO(BIAS) Off
(1) The active discharge remains on as long as VIN or VBIAS provide enough headroom for the discharge circuit to function.

VBIAS is not intended to be used dynamically when the IN rail is being powered up. If the BIAS rail is powered down when the IN rail is greater than 1.4 V, the PG output can trip. If the BIAS rail is powered up after the IN rail for VIN ≥ 1.4 V, a non-monotonic startup can occur.