SBVS395 July   2022 TPS7A57

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 7.3.4 Precision Enable and UVLO
      5. 7.3.5 Charge Pump Enable and BIAS Rail
      6. 7.3.6 Power-Good Pin (PG Pin)
      7. 7.3.7 Active Discharge
      8. 7.3.8 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Precision Enable (External UVLO)
      2. 8.1.2  Undervoltage Lockout (UVLO) Operation
        1. 8.1.2.1 IN Pin UVLO
        2. 8.1.2.2 BIAS UVLO
        3. 8.1.2.3 Typical UVLO Operation
        4. 8.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 8.1.3  Dropout Voltage (VDO)
      4. 8.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 8.1.5  Recommended Capacitor Types
      6. 8.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 8.1.7  Optimizing Noise and PSRR
      8. 8.1.8  Adjustable Operation
      9. 8.1.9  Load Transient Response
      10. 8.1.10 Current Limit and Foldback Behavior
      11. 8.1.11 Charge Pump Operation
      12. 8.1.12 Sequencing
      13. 8.1.13 Power-Good Functionality
      14. 8.1.14 Output Impedance
      15. 8.1.15 Paralleling for Higher Output Current and Lower Noise
      16. 8.1.16 Current Mode Margining
      17. 8.1.17 Voltage Mode Margining
      18. 8.1.18 Power Dissipation (PD)
      19. 8.1.19 Estimating Junction Temperature
      20. 8.1.20 TPS7A57EVM-081 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.14 Output Impedance

Output impedance can be modeled, as shown in Figure 8-13, as an ideal voltage source followed by a series R (ROUT) and series L (LOUT) output.

GUID-20220404-SS0I-HXF2-VX6C-XK6WBGV4G477-low.gif Figure 8-13 Output Impedance Model

Output impedance curves were measured using the EVM and are provided for the following conditions:

  1. Figure 8-14, Figure 8-15, and Figure 8-16 are provided for the 5.5-VIN, 5-VOUT, and IOUT = 200-mA, 500-mA, and 5-A conditions
  2. Figure 8-17 is provided for the 0.9-VIN, 0.5-VOUT, and IOUT = 4.6-A conditions
  3. Figure 8-18 to Figure 8-21 are provided for the 0.75 -VIN, 0.5-VOUT, 3-VBIAS, and IOUT = 20-mA, 200-mA, 500-mA, and 1-A conditions.

GUID-20220412-SS0I-FJTT-WGXC-XFHH6DPC6JS6-low.pngFigure 8-14 VIN = 5.5 V, VOUT = 5 V, VBIAS = 8 V, CP_EN = 0, IOUT = 200 mA
GUID-20220412-SS0I-L1F4-TXBQ-Q2H4XLTR6QPR-low.pngFigure 8-16 VIN = 5.5 V, VOUT = 5 V, VBIAS = 8 V, CP_EN = 0, IOUT = 5 A
GUID-20220412-SS0I-WK5C-SXSX-4F0ZNXCSW1HT-low.pngFigure 8-18 VIN = 0.75 V, VBIAS = 3 V, VOUT = 0.5 V , CP_EN = 0, IOUT = 20 mA
GUID-20220412-SS0I-HRBK-99NN-CLTFV0JTLWKH-low.pngFigure 8-20 VIN = 0.75 V, VBIAS = 3 V, VOUT = 0.5 V, CP_EN = 0, IOUT = 500 mA
GUID-20220412-SS0I-H5KD-ZZP8-GF58XWBRXDVR-low.pngFigure 8-15 VIN = 5.5 V, VOUT = 5 V, VBIAS = 8 V, CP_EN = 0, IOUT = 500 mA
GUID-20220412-SS0I-5XJ6-RSRR-Q6KVZRCQLWCD-low.pngFigure 8-17 VIN = 0.9 V, VBIAS = 3 V, VOUT = 0.5 V , CP_EN = 0, IOUT = 4.6 A
GUID-20220412-SS0I-90XX-6G6L-NTWQBFXF8DD1-low.pngFigure 8-19 VIN = 0.75 V, VBIAS = 3 V, VOUT = 0.5 V, CP_EN = 0, IOUT = 100 mA
GUID-20220412-SS0I-XSNF-STSB-CXT79XRDLHS1-low.pngFigure 8-21 VIN = 0.75 V, VBIAS = 3 V, VOUT = 0.5 V, CP_EN = 0, IOUT = 1 A

Table 8-6 provides a summary of the tested conditions described in this section.

Table 8-6 Model for Tested Conditions Summary
VIN VOUT VBIAS IOUT CP_EN ROUT LOUT
0.75 V 0.5 V 3 V 20 mA Off 200 μΩ 0.5 nH
0.75 V 0.5 V 3 V 200 mA Off 200 μΩ 0.5 nH
0.75 V 0.5 V 3 V 500 mA Off 200 μΩ 0.5 nH
0.75 V 0.5 V 3 V 1 A Off 200 μΩ 0.5 nH
0.9 V 0.5 V 3 V 4.6 A Off 200 μΩ 0.5 nH
5.5 V 5 V 8 V 200 mA Off 400 μΩ 0.5 nH
5.5 V 5 V 8 V 500 mA Off 300 μΩ 0.5 nH
5.5 V 5 V 8 V 5 A Off 200 μΩ 0.5 nH