SBVS395 July   2022 TPS7A57

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 7.3.4 Precision Enable and UVLO
      5. 7.3.5 Charge Pump Enable and BIAS Rail
      6. 7.3.6 Power-Good Pin (PG Pin)
      7. 7.3.7 Active Discharge
      8. 7.3.8 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Precision Enable (External UVLO)
      2. 8.1.2  Undervoltage Lockout (UVLO) Operation
        1. 8.1.2.1 IN Pin UVLO
        2. 8.1.2.2 BIAS UVLO
        3. 8.1.2.3 Typical UVLO Operation
        4. 8.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 8.1.3  Dropout Voltage (VDO)
      4. 8.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 8.1.5  Recommended Capacitor Types
      6. 8.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 8.1.7  Optimizing Noise and PSRR
      8. 8.1.8  Adjustable Operation
      9. 8.1.9  Load Transient Response
      10. 8.1.10 Current Limit and Foldback Behavior
      11. 8.1.11 Charge Pump Operation
      12. 8.1.12 Sequencing
      13. 8.1.13 Power-Good Functionality
      14. 8.1.14 Output Impedance
      15. 8.1.15 Paralleling for Higher Output Current and Lower Noise
      16. 8.1.16 Current Mode Margining
      17. 8.1.17 Voltage Mode Margining
      18. 8.1.18 Power Dissipation (PD)
      19. 8.1.19 Estimating Junction Temperature
      20. 8.1.20 TPS7A57EVM-081 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.20 TPS7A57EVM-081 Thermal Analysis

The TPS7A57EVM-081 was used to develop the TPS7A5701RTE thermal model. The RTE package is a 3-mm × 3-mm, 16-pin WQFN with 25-µm plating on each via. The EVM is a 3.5-inch × 3.5-inch (89 mm × 89 mm) PCB comprised of six layers. Table 8-9 lists the layer stackup for the EVM. Figure 8-29 to Figure 8-36 illustrate the various layer details for the EVM.

Table 8-9 TPS7A57EVM-081 PCB Stackup
LAYER NAME MATERIAL THICKNESS (mil)
1 Top overlay — —
2 Top solder Solder resist 0.4
3 Top layer Copper 2.756
4 Dielectric 1 FR-4 high Tg 9
5 Mid layer 1 Copper 2.756
6 Dielectric 2 FR-4 high Tg 9
7 Mid layer 2 Copper 2.756
8 Dielectric 3 FR-4 high Tg 9
9 Mid layer 3 Copper 2.756
10 Dielectric 4 FR-4 high Tg 9
11 Mid Layer 4 Copper 2.756
12 Dielectric 5 FR-4 high Tg 9
13 Bottom layer Copper 2.756
14 Bottom solder Solder resist 0.4
Figure 8-29 Top Assembly Layer and Silkscreen
Figure 8-31 Layer 2 Routing
Figure 8-33 Layer 4 Routing
Figure 8-35 Bottom Layer Routing
Figure 8-30 Top Layer Routing
Figure 8-32 Layer 3 Routing
Figure 8-34 Layer 5 Routing
Figure 8-36 Bottom Assembly Layer and Silkscreen

Table 8-10 shows thermal simulation data for the TPS7A57EVM-056. Figure 8-37 and Figure 8-38 show the thermal gradient on the PCB and device that results when a 1-W power dissipation is used through the pass transistor with a 25°C ambient temperature.

Table 8-10 TPS7A57EVM-081 Thermal Simulation Data
DUT RθJA(ͦ C/W) ⍦JB(ͦ C/W) ⍦JT(°C/W)
TPS7A57EVM-056 21.9 11.9 0.4
GUID-20220708-SS0I-WB72-CNG2-SSFPGVDJVBHB-low.gifFigure 8-37 TPS7A57EVM-081 3D View
GUID-20220406-SS0I-QVTN-NXT3-WNTGBK5QQXG2-low.gifFigure 8-38 TPS7A57EVM-081 PCB Thermal Gradient