SBVS395 July   2022 TPS7A57

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 7.3.4 Precision Enable and UVLO
      5. 7.3.5 Charge Pump Enable and BIAS Rail
      6. 7.3.6 Power-Good Pin (PG Pin)
      7. 7.3.7 Active Discharge
      8. 7.3.8 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Precision Enable (External UVLO)
      2. 8.1.2  Undervoltage Lockout (UVLO) Operation
        1. 8.1.2.1 IN Pin UVLO
        2. 8.1.2.2 BIAS UVLO
        3. 8.1.2.3 Typical UVLO Operation
        4. 8.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 8.1.3  Dropout Voltage (VDO)
      4. 8.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 8.1.5  Recommended Capacitor Types
      6. 8.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 8.1.7  Optimizing Noise and PSRR
      8. 8.1.8  Adjustable Operation
      9. 8.1.9  Load Transient Response
      10. 8.1.10 Current Limit and Foldback Behavior
      11. 8.1.11 Charge Pump Operation
      12. 8.1.12 Sequencing
      13. 8.1.13 Power-Good Functionality
      14. 8.1.14 Output Impedance
      15. 8.1.15 Paralleling for Higher Output Current and Lower Noise
      16. 8.1.16 Current Mode Margining
      17. 8.1.17 Voltage Mode Margining
      18. 8.1.18 Power Dissipation (PD)
      19. 8.1.19 Estimating Junction Temperature
      20. 8.1.20 TPS7A57EVM-081 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.16 Current Mode Margining

Output voltage margining is a technique that allows a circuit to be evaluated for how well changes are tolerated in the power supply. This test is typically performed by adjusting the supply voltage to a fixed percentage above and below its nominal output voltage.

This section discusses the implementation of a voltage margining application using the TPS7A57. A margining target of ±2.5% is used to demonstrate the chosen implementation.

Figure 8-23 shows a simplified visualization of the TPS7A57 REF pin with a current DAC.

GUID-20220401-SS0I-29KJ-J4VW-SD4MLJCMRM9T-low.gif Figure 8-23 Simplified Margining Schematic

Table 8-7 summarizes the design requirements.

Table 8-7 Design Requirement
PARAMETER Design Values
VIN 2.5 V
VOUT 1.8 V nominal with ±2.5% margining
CNR/SS 4.7 μF
RREF 36 kΩ
DAC IOUT range ±25 μA

In this example, the output voltage is set to a nominal 1.8 V using 36 kΩ at the REF pin to GND. Equation 12 calculates the RREF resistor value.

Equation 12. RREF = VOUT / IREF

The DAC63204, a 4-channel, 12-bit voltage and current output DAC with I2C, was selected and programmed into the current-output mode with an output range set to ±25 μA. In conjunction with the 8-bit current DAC resolution, this output range allows a minimum step size (or LSB) of approximately 196 nA. Into the 36-kΩ resistor, the LSB translates into a 7-mV voltage resolution or 0.38% of the nominal 1.8-V targeted voltage. To achieve the full ±2.5% swing around the nominal voltage, the DAC63204 must source or sink ±1.25 μA.

The current flowing through RREF changes to 51.25 μA and 48.75 μA and adjusts the output voltage to 1.845 V and 1.75 V, respectively.

Figure 8-24 and Figure 8-25 show the current margining results.

GUID-20220401-SS0I-JLK4-DQ57-TC7HZ9Z5RJR7-low.pngFigure 8-24 Margining Up
GUID-20220401-SS0I-F5DV-SGSS-MQ1LM01LL537-low.pngFigure 8-25 Margining Down

When implementing voltage margining with this LDO, a time constant is associated with its response. This RC time constant is a result of the parallel combination of RREF and CNR/SS, see Figure 8-23. This RC effect is illustrated in Figure 8-24 and Figure 8-25.

Equation 13 calculates the time constant for this implementation:

Equation 11. τ = RREF × CNR/SS

where:

  • RREF is 36 kΩ
  • CNR/SS is 4.7 μF
  • τ = 169 ms