SBVS395 July   2022 TPS7A57

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 7.3.4 Precision Enable and UVLO
      5. 7.3.5 Charge Pump Enable and BIAS Rail
      6. 7.3.6 Power-Good Pin (PG Pin)
      7. 7.3.7 Active Discharge
      8. 7.3.8 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Precision Enable (External UVLO)
      2. 8.1.2  Undervoltage Lockout (UVLO) Operation
        1. 8.1.2.1 IN Pin UVLO
        2. 8.1.2.2 BIAS UVLO
        3. 8.1.2.3 Typical UVLO Operation
        4. 8.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 8.1.3  Dropout Voltage (VDO)
      4. 8.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 8.1.5  Recommended Capacitor Types
      6. 8.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 8.1.7  Optimizing Noise and PSRR
      8. 8.1.8  Adjustable Operation
      9. 8.1.9  Load Transient Response
      10. 8.1.10 Current Limit and Foldback Behavior
      11. 8.1.11 Charge Pump Operation
      12. 8.1.12 Sequencing
      13. 8.1.13 Power-Good Functionality
      14. 8.1.14 Output Impedance
      15. 8.1.15 Paralleling for Higher Output Current and Lower Noise
      16. 8.1.16 Current Mode Margining
      17. 8.1.17 Voltage Mode Margining
      18. 8.1.18 Power Dissipation (PD)
      19. 8.1.19 Estimating Junction Temperature
      20. 8.1.20 TPS7A57EVM-081 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.7 Optimizing Noise and PSRR

Noise can be generally defined as any unwanted signal combining with the desired signal (such as the regulated LDO output) that results in degraded power-supply source quality. Noise can be easily noticed in audio as a hissing or popping sound. Extrinsic and intrinsic are the two basic groups that noise can be categorized into. Noise produced from an external circuit or natural phenomena such as 50 to 60 hertz power-line noise (spikes), along with its harmonics, is an excellent representative of extrinsic noise. Intrinsic noise is produced by components within the device circuitry such as resistors and transistors. For this device, the two dominating sources of intrinsic noise are the error amplifier and the internal reference voltage (VREF). Another term that sometimes combines with extrinsic noise is PSRR, which refers to the ability of the circuit or device to reject or filter out input supply noise and is expressed as a ratio of output voltage noise ripple to input voltage noise ripple.

Optimize the device intrinsic noise and PSRR by carefully selecting:

  • CNR/SS for the low-frequency range up to the device bandwidth
  • COUT for the high-frequency range close to and higher than the device bandwidth
  • Operating headroom, VIN – VOUT (VOpHr), mainly for the low-frequency range up to the device bandwidth, but also for higher frequencies to a less effect

The device noise performance can be significantly improved by using a larger CNR/SS capacitor to filter out noise coupling from the input into the device VREF reference. This coupling is especially apparent from low frequencies up to the device bandwidth. The low-pass filter formed by CNR/SS and RREF can be designed to target low-frequency noise originating in the input supply. One downside of a larger CNR/SS capacitor is a longer start-up time. The device unity-gain configuration eliminates the noise performance degradation that other LDOs suffer from because of their feedback network. Furthermore, increasing the device load current has little to no effect on the device noise performance.

Further improvement to the device noise at a higher frequency range than the device bandwidth can be achieved by using a larger COUT capacitor. However, a larger COUT increases inrush current and slows down the device transient response.

These behaviors are described in the Section 6.6 section. Figure 6-17 and Figure 6-19 list the measured 10-Hz to 100-kHz RMS noise for a 5-V device and a 0.5-V output voltage with a 300-mV headroom for different CNR/SS and COUT conditions with a 5-A load current. Table 8-2 and Table 8-3 list the typical output noise for these capacitors.

Increasing the operational headroom between VIN and VOUT has little to no effect on improving noise performance. However, this increase does improve PSRR significantly for frequency ranges up to the device bandwidth. Higher headroom can also improve transient performance of the device as well. Although COUT has little to no affect on improving PSRR at low frequency, COUT can improve PSRR for higher frequencies beyond the device bandwidth. A larger COUT can also lengthen start-up time and increase start-up inrush current. A combination of capacitors, such as 470 μF || 22 μF is more effective because a combination provides lower ESR and ESL. This behavior is illustrated in Figure 6-12.

Table 8-2 Output Noise for 0.5-VOUT vs COUT, and Typical Start-Up Time
Vn (μVRMS), 10-Hz to 100-kHz BW CNR/SS (µF) COUT (µF) START-UP TIME (ms)
2.4 4.7 22 11.75
2.48 4.7 470 11.75
Table 8-3 Output Noise for 5-VOUT vs CNR/SS, COUT, and Typical Start-Up Time for VCP_EN = 5.3 V
Vn (μVRMS), 10-Hz to 100-kHz BW CNR/SS (µF) COUT (µF) START-UP TIME (ms)
16.68 0.1 22 2.5
3.38 1 22 25
2.51 4.7 22 117.5