SLVSA62J March   2010  – March 2020 TPS7A60-Q1 , TPS7A61-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Programmable Reset Delay Option
      2.      Enable Option
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Reset Delay and Reset Output
      2. 8.3.2 Charge Pump Operation
      3. 8.3.3 Undervoltage Shutdown
      4. 8.3.4 Low-Voltage Tracking
      5. 8.3.5 Integrated Fault Protection
      6. 8.3.6 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode
      2. 8.4.2 Sleep Mode (TPS7A61-Q1 Only)
      3. 8.4.3 Regulation Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS7A60-Q1 Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Capacitor
          2. 9.2.1.2.2 Output Capacitor
        3. 9.2.1.3 Application Curve
      2. 9.2.2 TPS7A61-Q1 Typical Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Dissipation and Thermal Considerations
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1.1 Power Dissipation and Thermal Considerations

Power dissipated in the device can be calculated using Equation 2.

Equation 2. TPS7A60-Q1 TPS7A61-Q1 eq02-Pd_SLVSA62.gif

where

  • PD = continuous power dissipation
  • IOUT = output current
  • VIN = input voltage
  • VOUT = output voltage
  • IQUIESCENT = quiescent current

As IQUIESCENT << IOUT, therefore, the term IQUIESCENT × VIN in Equation 2 can be ignored.

For a device under operation at a given ambient air temperature (TA), the junction temperature (TJ) can be calculated using Equation 3.

Equation 3. TPS7A60-Q1 TPS7A61-Q1 eq03-Tj_SLVSA62.gif

where

  • RθJA = junction-to-ambient-air thermal impedance

The rise in junction temperature due to power dissipation can be calculated using Equation 4.

Equation 4. TPS7A60-Q1 TPS7A61-Q1 eq04-deltaT_SLVSA62.gif

For a given maximum junction temperature (TJ-Max), the maximum ambient air temperature (TA-Max) at which the device can operate can be calculated using Equation 5.

Equation 5. TPS7A60-Q1 TPS7A61-Q1 eq05-Tamax_SLVSA62.gif

Example:

If IOUT = 100 mA, VOUT = 5 V, VIN = 14 V, IQUIESCENT = 250 µA and RθJA= 30˚C/W, the continuous power dissipated in the device is 0.9 W. The rise in junction temperature due to power dissipation is 27˚C. For a maximum junction temperature of 150˚C, maximum ambient air temperature at which the device can operate is 123˚C.

For adequate heat dissipation, it is recommended to solder the thermal pad (exposed heat sink) to a thermal land pad on the PCB. Doing this provides a heat conduction path from the die to the PCB and reduces overall package thermal resistance. Power derating curves for the TPS7A60-Q1 and TPS7A61-Q1 family of devices in the KTT (TO-263) and KVU (TO-252) packages are shown in Figure 26.

TPS7A60-Q1 TPS7A61-Q1 power_derating_lvsa62.gifFigure 26. Power Derating Curves

For optimum thermal performance, TI recommends to use a high-K PCB with thermal vias between the ground plane and solder pad or thermal land pad. This is shown in Figure 27 (a) and (b). Further, the heat-spreading capabilities of a PCB can be considerably improved by using a thicker ground plane and a thermal land pad with a larger surface area.

TPS7A60-Q1 TPS7A61-Q1 multilayer_pcb_thermal_vias_lvsa62.gifFigure 27. Using Multilayer PCB and Thermal Vias For Adequate Heat Dissipation

Keeping other factors constant, surface area of the thermal land pad contributes to heat dissipation only to a certain extent. Figure 28 shows the variation of RθJA with surface area of the thermal land pad (soldered to the exposed pad) for KTT and KVU packages.

TPS7A60-Q1 TPS7A61-Q1 thetaja_vs_thermal_pad_area_lvsa62.gifFigure 28. RθJA vs Thermal Pad Area