SLVSA98F May   2010  – March 2020 TPS7A65-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
      2.      Typical Regulator Stability
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dissipation Ratings
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Up
      2. 7.3.2 Charge-Pump Operation
      3. 7.3.3 Low-Power Mode
      4. 7.3.4 Undervoltage Shutdown
      5. 7.3.5 Low-Voltage Tracking
      6. 7.3.6 Integrated Fault Protection
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN Lower Than 4 V
      2. 7.4.2 Operation With VIN Larger Than 4 V
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Dissipation and Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1.1 Power Dissipation and Thermal Considerations

Calculate the power dissipated in the device using Equation 1.

Equation 1. PD = IOUT × (VIN - VOUT)) + IQUIESCENT × VIN

where

  • PD = continuous power dissipation
  • IOUT = output current
  • VIN = input voltage
  • VOUT = output voltage
  • IQUIESCENT = quiescent current.

IQUIESCENT << IOUT; therefore, ignore the term IQUIESCENT × VIN in Equation 1.

For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ) using Equation 2.

Equation 2. TJ = TA + (θJA × PD)

where

  • θJA = junction-to-ambient air thermal impedance.

Calculate the rise in junction temperature due to power dissipation using Equation 3.

Equation 3. ΔT = TJ – TA = (θJA × PD)

For a given maximum junction temperature (TJ-Max), calculate the maximum ambient air temperature (TA-Max) at which the device can operate using Equation 4.

Equation 4. TA-Max = TJ-Max – (θJA × PD)

Example

If IOUT = 100 mA, VOUT = 5 V, VIN = 14 V, IQUIESCENT = 250 µA and θJA= 30˚C/W, the continuous power dissipated in the device is 0.9 W. The rise in junction temperature due to power dissipation is 27˚C. For a maximum junction temperature of 150˚C, maximum ambient air temperature at which the device can operate is 123˚C.

For adequate heat dissipation, TI recommends soldering the power pad (exposed heat sink) to the thermal land pad on the PCB. Doing this provides a heat conduction path from the die to the PCB and reduces overall package thermal resistance. Figure 22 shows power derating curves for the TPS7A65-Q1 family of devices in the KVU (DPAK) package.

TPS7A65-Q1 power_derating_lvsa98.gifFigure 22. Power Derating Curves

For optimum thermal performance, TI recommends using a high-K PCB with thermal vias between the ground plane and solder pad or thermal land pad. Figure 23 (a) and (b) show this. Further, a design can improve the heat-spreading capabilities of a PCB considerably by using a thicker ground plane and a thermal land pad with a larger surface area.

TPS7A65-Q1 multilayer_pcb_thermal_vias_lvsa98.gifFigure 23. Using a Multilayer PCB and Thermal Vias for Adequate Heat Dissipation

Keeping other factors constant, the surface area of the thermal land pad contributes to heat dissipation only to a certain extent. Figure 24 shows the variation of θJA with surface area of the thermal land pad (soldered to the exposed pad) for the KVU package.

TPS7A65-Q1 thetaja_vs_thermal_pad_area_lvsa98.gifFigure 24. θJA vs Thermal Pad Area