SBVS416B May   2022  – August 2022 TPS7A74

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Shutdown
      2. 7.3.2 Active Discharge
      3. 7.3.3 Global Undervoltage Lockout (UVLO) Circuit
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
    5. 7.5 Programming
      1. 7.5.1 Programmable Soft-Start
      2. 7.5.2 Sequencing Requirements
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Input, Output, and Bias Capacitor Requirements
      3. 8.1.3 Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Output Noise
      6. 8.1.6 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 FPGA I/O Supply at 1.8 V With a Bias Rail
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Estimating Junction Temperature
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.1 Adjusting the Output Voltage

Figure 8-1 shows the typical application circuit for the adjustable output device.

GUID-20220316-SS0I-B6BR-KZQ9-7R4BWDQLVHJC-low.gif Figure 8-1 Typical Application Circuit for the TPS7A74 (Adjustable)

R1 and R2 can be calculated for any output voltage using the formula shown in Figure 8-1. Table 8-1 lists sample resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R2 must be ≤ 4.99 kΩ.

Table 8-1 Standard 1% Resistor Values for Programming the Output Voltage(1)
R1 (kΩ) R2 (kΩ) Targeted VOUT (V)
Short Open 0.65
0.768 4.99 0.75
2.43 4.53 1.00
2.72 4.42 1.05
3.48 4.99 1.10
4.22 4.99 1.20
4.99 3.83 1.50
4.99 2.80 1.80
4.99 1.74 2.51
4.99 1.21 3.33
(1) VOUT = 0.65 × (1 + R1 / R2).

 

Note:

When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately 50 μA of current from OUT. Although this condition does not cause any damage to the device, the output current can charge the OUT node if total resistance between OUT and GND (including external feedback resistors) is greater than 10 kΩ.

Because this LDO has a relatively low quiescent current of 50 μA, some applications may benefit from using larger R1 and R2 resistor values. In such cases where resistor values greater than 5 kΩ are considered, adding a Cff capacitor across R1 may help improve stability.