SBVS416B
May 2022 – August 2022
TPS7A74
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Enable and Shutdown
7.3.2
Active Discharge
7.3.3
Global Undervoltage Lockout (UVLO) Circuit
7.3.4
Internal Current Limit
7.3.5
Thermal Shutdown Protection (TSD)
7.4
Device Functional Modes
7.4.1
Normal Operation
7.4.2
Dropout Operation
7.4.3
Disabled
7.5
Programming
7.5.1
Programmable Soft-Start
7.5.2
Sequencing Requirements
8
Application and Implementation
8.1
Application Information
8.1.1
Adjusting the Output Voltage
8.1.2
Input, Output, and Bias Capacitor Requirements
8.1.3
Transient Response
8.1.4
Dropout Voltage
8.1.5
Output Noise
8.1.6
Estimating Junction Temperature
8.2
Typical Application
8.2.1
FPGA I/O Supply at 1.8 V With a Bias Rail
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.1.1
Estimating Junction Temperature
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Device Support
9.1.1
Development Support
9.1.1.1
Evaluation Modules
9.1.1.2
Spice Models
9.2
Documentation Support
9.2.1
Related Documentation
9.3
Receiving Notification of Documentation Updates
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DSD|8
MPDS238B
Thermal pad, mechanical data (Package|Pins)
DSD|8
QFND348B
Orderable Information
sbvs416b_oa
sbvs416b_pm
8.4.2
Layout Example
Figure 8-7
Example Layout (DSD Package)