SBVS416B May   2022  – August 2022 TPS7A74

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Shutdown
      2. 7.3.2 Active Discharge
      3. 7.3.3 Global Undervoltage Lockout (UVLO) Circuit
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
    5. 7.5 Programming
      1. 7.5.1 Programmable Soft-Start
      2. 7.5.2 Sequencing Requirements
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Input, Output, and Bias Capacitor Requirements
      3. 8.1.3 Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Output Noise
      6. 8.1.6 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 FPGA I/O Supply at 1.8 V With a Bias Rail
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Estimating Junction Temperature
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.4 Dropout Voltage

The TPS7A74 offers very low dropout performance, making the device well-suited for high-current, low VIN and low VOUT applications. The low dropout allows the device to be used in place of a dc/dc converter and still achieve good efficiency. Equation 6 provides a quick estimate of the efficiency.

Equation 6. GUID-BF544CC5-D4B0-4BC6-9DF2-8DE9C69F43DC-low.gif

This efficiency provides designers with the power architecture for their applications to achieve the smallest, simplest, and lowest cost solutions.

For this architecture, there are two different specifications for dropout voltage. The first specification (see Figure 8-2) is referred to as VIN dropout and is used when an external bias voltage is applied to achieve low dropout. This specification assumes that VBIAS is at least 2.8 V above VOUT, which is the case for VBIAS when powered by a 5.0-V rail with 5% tolerance and with VOUT = 1.5 V. If VBIAS is higher than VOUT + 2.8 V, the VIN dropout is less than specified.

Note: 2.8 V is a test condition of this device and can be adjusted by referring to the Section 6.5 table.

The second specification (illustrated in Figure 8-2) is referred to as VBIAS dropout and applies to applications where IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because VBIAS provides the gate drive to the pass transistor; therefore, VBIAS must be 1.3 V above VOUT. Because of this usage, having IN and BIAS tied together become a highly inefficient solution that can consume large amounts of power. Pay attention not to exceed the power rating of the device package.