SBVS179B December   2011  – August 2015 TPS7A8101

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Start-Up
      4. 7.3.4 Undervoltage Lock-Out (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Component Values
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Dropout Voltage
        2. 8.2.1.2 Minimum Load
        3. 8.2.1.3 Input and Output Capacitor Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Noise
        2. 8.2.2.2 Transient Response
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Thermal Protection
    4. 10.4 Power Dissipation
    5. 10.5 Estimating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).(1)
MIN MAX UNIT
Voltage IN –0.3 7 V
FB, NR –0.3 3.6
EN –0.3 VIN + 0.3(2)
OUT –0.3 7
Current OUT Internally Limited A
Temperature Operating virtual junction, TJ –55 150 °C
Storage, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) VEN absolute maximum rating is VIN + 0.3 V or +7 V, whichever is smaller.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VI Input voltage 2.2 6.5 V
IO Output current 0 1 A
TA Operating free air temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS7A8101 UNIT
DRV (SON)
8 PINS
RθJA Junction-to-ambient thermal resistance 47.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.9 °C/W
RθJB Junction-to-board thermal resistance 23.4 °C/W
ψJT Junction-to-top characterization parameter 1 °C/W
ψJB Junction-to-board characterization parameter 23.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 1 mA, VEN = 2.2 V, COUT = 4.7 μF, CNR = 0.01 μF, and CBYPASS = 0 μF, unless otherwise noted. TPS7A8101 is tested at VOUT = 0.8 V and VOUT = 6 V. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range(1) 2.2 6.5 V
VNR Internal reference 0.79 0.8 0.81 V
VOUT Output voltage range 0.8 6 V
Output accuracy(2) VOUT + 0.5 V ≤ VIN ≤ 6 V, VIN ≥ 2.5 V,
100 mA ≤ IOUT ≤ 500 mA, 0°C ≤ TJ ≤ 85°C		 -2% 2%
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V,
100 mA ≤ IOUT ≤ 1 A		 –3% ±0.3% 3%
ΔVO(ΔVI) Line regulation VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V,
IOUT = 100 mA		 150 μV/V
ΔVO(ΔIL) Load regulation 100 mA ≤ IOUT ≤ 1 A 2 μV/mA
VDO Dropout voltage(3) VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V,
IOUT = 500 mA, VFB = GND or VSNS = GND		 250 mV
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V,
IOUT = 750 mA, VFB = GND or VSNS = GND		 350
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V,
IOUT = 1 A, VFB = GND or VSNS = GND		 500
ILIM Output current limit VOUT = 0.85 × VOUT(NOM), VIN ≥ 3.3 V 1100 1400 2000 mA
IGND Ground pin current IOUT = 1 mA 60 100 μA
IOUT = 1 A 350
ISHDN Shutdown current (IGND) VEN ≤ 0.4 V, VIN ≥ 2.2 V, RL = 1 kΩ,
0°C ≤ TJ ≤ 85°C		 0.2 2 μA
IFB Feedback pin current VIN = 6.5 V, VFB = 0.8 V 0.02 1 μA
PSRR Power-supply rejection ratio VIN = 4.3 V, VOUT = 3.3 V,
IOUT = 750 mA		 f = 100 Hz 80 dB
f = 1 kHz 82
f = 10 kHz 78
f = 100 kHz 60
f = 1 MHz 54
Vn Output noise voltage BW = 100 Hz to 100 kHz,
VIN = 3.8 V, VOUT = 3.3 V,
IOUT = 100 mA, CNR = CBYPASS = 470 nF		 23.5 μVRMS
VEN(HI) Enable high (enabled) 2.2 V ≤ VIN ≤ 3.6 V, RL = 1 kΩ 1.2 V
3.6 V < VIN ≤ 6.5 V, RL = 1 kΩ 1.35
VEN(LO) Enable low (shutdown) RL = 1 kΩ 0 0.4 V
IEN(HI) Enable pin current, enabled VIN = VEN = 6.5 V 0.02 1 μA
tSTR Start-up time VOUT(NOM) = 3.3 V, VOUT = 0% to 90% VOUT(NOM),
RL = 3.3 kΩ, COUT = 10 μF, CNR = 470 nF		 80 ms
UVLO Undervoltage lockout VIN rising, RL = 1 kΩ 1.86 2 2.10 V
Hysteresis VIN falling, RL = 1 kΩ 75 mV
TSD Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140 °C
TJ Operating junction temperature –40 125 °C
(1) Minimum VIN = VOUT + VDO or 2.2 V, whichever is greater.
(2) The TPS7A8101 does not include external resistor tolerances and it is not tested at this condition: VOUT = 0.8 V, 4.5V ≤ VIN ≤ 6.5 V, and 750 mA ≤ IOUT ≤ 1 A because the power dissipation is greater than the maximum rating of the package.
(3) VDO is not measured for fixed output voltage devices with VOUT < 1.7 V because minimum VIN = 2.2 V.

6.6 Typical Characteristics

At VOnom = 3.3 V, VI = VOnom + 0.5 V or 2.2 V (whichever is greater), IO = 100 mA, V(EN) = VI, C(IN) = 1 μF, C(OUT) = 4.7 μF, and C(NR) = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
TPS7A8101 tc_load_reg_slvsck0.gif
NOTE: The Y-axis shows 1% VO per division
Figure 1. Load Regulation
TPS7A8101 tc_line_reg_slvsck0.gif
VO = 0.8 V IO = 750 mA
NOTE: The Y-axis shows 1% VO per division
Figure 3. Line Regulation
TPS7A8101 tc_vdo-vin_1a_slvsck0.gif
IO = 1 A
Figure 5. Dropout Voltage vs Input Voltage
TPS7A8101 tc_vdo-vin_500ma_slvsck0.gif
IO = 500 mA
Figure 7. Dropout Voltage vs Input Voltage
TPS7A8101 tc_vdo-tmp_slvsck0.gif
VI = 3.6 V
Figure 9. Dropout Voltage vs Temperature
TPS7A8101 tc_ignd-iout_slvsck0.gif
Figure 11. Ground Pin Current vs Load Current
TPS7A8101 tc_ilim-tmp_slvsck0.gif
VO = VI – 0.5 V
Figure 13. Current Limit vs Temperature
TPS7A8101 D002_SLVSCK0.gif
VI – VO = 1 V C(IN) = 0 F C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF
Figure 15. PSRR vs Frequency
TPS7A8101 D004_SLVSCK0.gif
VI – VO = 1 V C(IN) = 0 F C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF
Figure 17. PSRR vs Frequency
TPS7A8101 tc_psrr-vdo_100ma_slvsck0.gif
IO = 100 mA C(IN) = 0 F
Figure 19. PSRR vs Dropout Voltage
TPS7A8101 D006_SLVSCK0.gif
VI – VO = 0.5 V C(OUT) = 10 µF C(IN) = 10 µF
24.09 µVRMS (C(NR) = C(BYPASS) = 100 nF)
23.54 µVRMS (C(NR) = C(BYPASS) = 470 nF)
Figure 21. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))
TPS7A8101 D008_SLVSCK0.gif
23.54 µVRMS (IO = 100 mA) C(IN) = 10 µF VI – VO = 0.5 V
23.71 µVRMS (IO = 750 mA) C(NR) = 470 nF C(OUT) = 10 µF
22.78 µVRMS (IO = 1 A) C(BYPASS) = 470 nF
Figure 23. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))
TPS7A8101 D010_SLVSCK0.gif
Using the same value of C(NR) and C(BYPASS) in the X-Axis
Figure 25. Start-up Time vs Noise Reduction Capacitance
TPS7A8101 tc_load_trans_slvsck0.gif
IO = 100 mA → 1 A → 100 mA
Figure 27. Load Transient Response
TPS7A8101 D012_SLVSCK0.gif
RL = 33 Ω C(NR) = 470 nF C(BYPASS) = 470 nF
C(OUT) = 10 µF C(IN) = 10 µF
(1) The internal reference requires approximately 80 ms of rampup time (see Start-Up) from the enable event; therefore, VO fully reaches the target output voltage of 3.3 V in 80 ms from start-up.
Figure 29. Power-Up and Power-Down Response
TPS7A8101 tc_load_reg_light_slvsck0.gif
NOTE: The Y-axis shows 1% VO per division
Figure 2. Load Regulation Under Light Loads
TPS7A8101 tc_line_reg_light_slvsck0.gif
VO = 0.8 V IO = 5 mA
NOTE: The Y-axis shows 1% VO per division
Figure 4. Line Regulation Under Light Loads
TPS7A8101 tc_vdo-vin_750ma_slvsck0.gif
IO = 750 mA
Figure 6. Dropout Voltage vs Input Voltage
TPS7A8101 tc_vdo-iout_slvsck0.gif
VI = 3.6 V
Figure 8. Dropout Voltage vs Load Current
TPS7A8101 tc_ignd-vin_slvsck0.gif
VO = 0.8 V IO = 750 mA
Figure 10. Ground Pin Current vs Input Voltage
TPS7A8101 tc_ishdn-tmp_slvsck0.gif
V(EN) = 0.4 V
Figure 12. Shutdown Current vs Temperature
TPS7A8101 D001_SLVSCK0.gif
C(NR) = C(BYPASS) = 470 nF C(OUT) = 10 µF C(IN) = 0 F
Figure 14. PSRR vs Frequency
TPS7A8101 D003_SLVSCK0.gif
VI – VO = 0.5 V C(IN) = 0 F C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF
Figure 16. PSRR vs Frequency
TPS7A8101 D005_SLVSCK0.gif
VI – VO = 0.5 V C(IN) = 0 F C(OUT) = 10 µF
C(NR) = C(BYPASS) = 470 nF
Figure 18. PSRR vs Frequency
TPS7A8101 tc_psrr-vdo_750ma_slvsck0.gif
IO = 750 mA C(IN) = 0 F
Figure 20. PSRR vs Dropout Voltage
TPS7A8101 D007_SLVSCK0.gif
25.89 µVRMS (VO = 1.8 V) C(IN) = 10 µF VI – VO = 0.5 V
23.54 µVRMS (VO = 2.5 V) C(NR) = 470 nF C(OUT) = 10 µF
23.54 µVRMS (VO = 3.3 V) C(BYPASS) = 470 nF
Figure 22. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))
TPS7A8101 D009_SLVSCK0.gif
23.54 µVRMS (CO = 10 µF) C(IN) = 10 µF VI – VO = 0.5 V
23.91 µVRMS (CO = 22 µF) C(NR) = 470 nF C(OUT) = 10 µF
22.78 µVRMS (CO = 100 µF) C(BYPASS) = 470 nF
Figure 24. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))
TPS7A8101 tc_line_trans_slvsck0.gif
VI = 3.8 V → 4.8 V → 3.8 V
IO = 500 mA
Figure 26. Line Transient Response
TPS7A8101 D011_SLVSCK0.gif
RL = 33 Ω C(NR) = 470 nF C(BYPASS) = 470 nF
C(OUT) = 10 µF C(IN) = 10 µF
Figure 28. Enable Pulse Response, see (1) in Figure 29