SBVS304B June 2017 – October 2021 TPS7A83A
PRODUCTION DATA
The output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CNR/SS). This soft-start eliminates power-up initialization problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also reduces peak inrush current during start-up, thus minimizing start-up transients to the input power bus.
The output voltage (VOUT) rises proportionally to VNR/SSduring start-up as the LDO regulates so that the feedback voltage equals the NR/SS voltage (VFB = VNR/SS). As such, the time required for VNR/SS to reach its nominal value determines the rise time of VOUT (start-up time).
Not using a noise-reduction capacitor on the NR/SS pin can result in output voltage overshoot of approximately 10%. Using a capacitor on the NR/SS pin minimizes the overshoot.