The UVLO circuit ensures that the device stays disabled before its input or bias supplies reach the minimum operational voltage range, and ensures that the device shuts down when the input supply or bias supply collapse.

The UVLO circuit has a minimum response time of several microseconds to fully assert. During this time, a downward line transient below approximately 0.8 V causes the UVLO to assert for a short time; however, the UVLO circuit does not have enough stored energy to fully discharge the internal circuits inside of the device. When the UVLO circuit does not fully discharge, the internal circuits of the output are not fully disabled.

The effect of the downward line transient can be mitigated by either using a larger input capacitor to limit the fall time of the input supply when operating near the minimum V_IN, or by using a bias rail.

Figure 8-8 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the following parts:

• Region A: The device does not turn on until the input reaches the UVLO rising threshold.
• Region B: Normal operation with a regulated output
• Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The output may fall out of regulation but the device is still enabled.
• Region D: Normal operation with a regulated output
• Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising threshold is reached by the input voltage and a normal start-up then follows.
• Region F: Normal operation followed by the input falling to the UVLO falling threshold.
• Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The output falls because of the load and active discharge circuit.

Figure 8-8 Typical UVLO Operation