SBVS233B January   2016  – June 2021 TPS7A84

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Low-Noise, High-PSRR Output
      2. 7.3.2  Integrated Resistance Network (ANY-OUT)
      3. 7.3.3  Bias Rail
      4. 7.3.4  Power-Good Function
      5. 7.3.5  Programmable Soft-Start
      6. 7.3.6  Internal Current Limit (ILIM)
      7. 7.3.7  Enable
      8. 7.3.8  Active Discharge Circuit
      9. 7.3.9  Undervoltage Lockout (UVLO)
      10. 7.3.10 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with 1.1 V ≤ VIN < 1.4 V
      2. 7.4.2 Operation with 1.4 V ≤ VIN ≤ 6.5 V
      3. 7.4.3 Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Recommended Capacitor Types
      2. 8.1.2  Input and Output Capacitor Requirements (CIN and COUT)
      3. 8.1.3  Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      4. 8.1.4  Feed-Forward Capacitor (CFF)
      5. 8.1.5  Soft-Start and In-Rush Current
      6. 8.1.6  Optimizing Noise and PSRR
      7. 8.1.7  Charge Pump Noise
      8. 8.1.8  ANY-OUT Programmable Output Voltage
      9. 8.1.9  ANY-OUT Operation
      10. 8.1.10 Increasing ANY-OUT Resolution for LILO Conditions
      11. 8.1.11 Current Sharing
      12. 8.1.12 Adjustable Operation
      13. 8.1.13 Sequencing Requirements
        1. 8.1.13.1 Sequencing with a Power-Good DC-DC Converter Pin
        2. 8.1.13.2 Sequencing with a Microcontroller (MCU)
      14. 8.1.14 Power-Good Operation
      15. 8.1.15 Undervoltage Lockout (UVLO) Operation
      16. 8.1.16 Dropout Voltage (VDO)
      17. 8.1.17 Behavior when Transitioning from Dropout into Regulation
      18. 8.1.18 Load Transient Response
      19. 8.1.19 Negatively-Biased Output
      20. 8.1.20 Reverse Current Protection
      21. 8.1.21 Power Dissipation (PD)
      22. 8.1.22 Estimating Junction Temperature
      23. 8.1.23 Recommended Area for Continuous Operation (RACO)
    2. 8.2 Typical Applications
      1. 8.2.1 Low-Input, Low-Output (LILO) Voltage Conditions
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application for a 5.0-V Rail
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.4 V (whichever is greater), VBIAS = open, VOUT(nom) = 0.8 V(2), OUT connected to 50 Ω to GND(3), VEN = 1.1 V, CIN = 10 μF, COUT = 47 μF, CNR/SS without CFF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input supply voltage range(1) 1.1 6.5 V
VBIAS Bias supply voltage range(1) VIN = 1.1 V 3.0 6.5 V
VFB Feedback voltage 0.8 V
VNR/SS NR/SS pin voltage 0.8 V
VUVLO1(IN) Input supply UVLO with BIAS VIN rising with VBIAS = 3.0 V 1.02 1.085 V
VHYS1(IN) VUVLO1(IN) hysteresis VBIAS = 3.0 V 320 mV
VUVLO2(IN) Input supply UVLO without BIAS VIN rising 1.31 1.39 V
VHYS2(IN) VUVLO2(IN) hysteresis 253 mV
VUVLO(BIAS) Bias supply UVLO VBIAS rising, VIN = 1.1 V 2.83 2.9 V
VHYS(BIAS) VUVLO(BIAS) hysteresis VIN = 1.1 V 290 mV
VOUT Output voltage Range Using the ANY-OUT pins 0.8 – 1.0% 3.95 + 1.0% V
Using external resistors(4) 0.8 – 1.0% 5.0 + 1.0%
Accuracy(4)(5) 0.8 V ≤ VOUT ≤ 5 V, 5 mA ≤ IOUT ≤ 3 A, over VIN –1.0% 1.0%
Accuracy with BIAS VIN = 1.1 V, 5 mA ≤ IOUT ≤ 3 A,
3.0 V ≤ VBIAS ≤ 6.5 V		 –0.75% 0.75%
ΔVOUT/
ΔVIN		 Line regulation IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V 0.0035 mV/V
ΔVOUT/
ΔIOUT		 Load regulation 5 mA ≤ IOUT ≤ 3 A, 3.0 V ≤ VBIAS ≤ 6.5 V,
VIN = 1.1 V		 0.07 mV/A
5 mA ≤ IOUT ≤ 3 A 0.08
5 mA ≤ IOUT ≤ 3 A, VOUT = 5.0 V 0.4
VDO Dropout voltage VIN = 1.4 V, IOUT = 3 A, VFB = 0.8 V – 3% 156 250 mV
VIN = 5.4 V, IOUT = 3 A, VFB = 0.8 V – 3% 220 340
VIN = 1.1 V, VBIAS = 5.0 V,
IOUT = 3 A, VFB = 0.8 V – 3%		 110 180
ILIM Output current limit VOUT forced at 0.9 × VOUT(nom),
VIN = VOUT(nom) + 0.4 V		 3.7 4.2 4.7 A
ISC Short-circuit current limit RLOAD = 20 mΩ 1.0 A
IGND GND pin current VIN = 6.5 V, IOUT = 5 mA 2.8 4 mA
VIN = 1.4 V, IOUT = 3 A 4.2 5.5
Shutdown, PG = open, VIN = 6.5 V, VEN = 0.5 V 25 µA
IEN EN pin current VIN = 6.5 V, VEN = 0 V and 6.5 V –0.1 0.1 µA
IBIAS BIAS pin current VIN = 1.1 V, VBIAS = 6.5 V,
VOUT(nom) = 0.8 V, IOUT = 3 A		 2.3 3.5 mA
VIL(EN) EN pin low-level input voltage
(disable device)		 0 0.5 V
VIH(EN) EN pin high-level input voltage
(enable device)		 1.1 6.5 V
VIT(PG) PG pin threshold For falling VOUT 82% × VOUT 88.3% × VOUT 93% × VOUT V
VHYS(PG) PG pin hysteresis For rising VOUT 1% × VOUT V
VOL(PG) PG pin low-level output voltage VOUT < VIT(PG), IPG = –1 mA
(current into device)		 0.4 V
Ilkg(PG) PG pin leakage current VOUT > VIT(PG), VPG = 6.5 V 1 µA
INR/SS NR/SS pin charging current VNR/SS = GND, VIN = 6.5 V 4.0 6.2 9.0 µA
IFB FB pin leakage current VIN = 6.5 V –100 100 nA
PSRR Power-supply ripple rejection VIN – VOUT = 0.4 V,
IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT =
47 μF || 10 μF || 10 μF		 f = 10 kHz,
VOUT = 0.8 V,
VBIAS = 5.0 V		 42 dB
f = 500 kHz, VOUT = 0.8 V, VBIAS = 5.0 V 39
f = 10 kHz,
VOUT = 5.0 V		 40
f = 500 kHz, VOUT = 5.0 V 25
Vn Output noise voltage BW = 10 Hz to 100 kHz, VIN = 1.1 V,
VOUT = 0.8 V, VBIAS = 5.0 V, IOUT = 3 A,
CNR/SS = 100 nF, CFF = 10 nF,
COUT = 47 μF || 10 μF || 10 μF		 4.4 μVRMS
BW = 10 Hz to 100 kHz,
VOUT = 5.0 V, IOUT = 3 A, CNR/SS = 100 nF,
CFF = 10 nF, COUT = 47 μF || 10 μF || 10 μF		 7.7
Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140
TJ Operating junction temperature –40 125 °C
(1) BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is required when the VIN supply is higher than or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for VIN ≤ 2.2 V.
(2) VOUT(nom) is the calculated VOUT target value from the ANY-OUT in a fixed configuration. In an adjustable configuration, VOUT(nom) is the expected VOUT value set by the external feedback resistors.
(3) This 50-Ω load is disconnected when the test conditions specify an IOUT value.
(4) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
(5) The device is not tested under conditions where VIN > VOUT + 1.7 V and IOUT = 3 A, because the power dissipation is higher than the maximum rating of the package.