SBVS313 June   2017 TPS7A85A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation Features
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 System Start-Up Features
        1. 7.3.2.1 Programmable Soft Start (NR/SS)
        2. 7.3.2.2 Internal Sequencing
          1. 7.3.2.2.1 Enable (EN)
          2. 7.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 7.3.2.2.3 Active Discharge
        3. 7.3.2.3 Power-Good Output (PG)
      3. 7.3.3 Internal Protection Features
        1. 7.3.3.1 Foldback Current Limit (ICL)
        2. 7.3.3.2 Thermal Protection (Tsd)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection
        1. 8.1.1.1 Adjustable Operation
        2. 8.1.1.2 ANY-OUT Programmable Output Voltage
        3. 8.1.1.3 ANY-OUT Operation
        4. 8.1.1.4 Increasing ANY-OUT Resolution for LILO Conditions
        5. 8.1.1.5 Current Sharing
        6. 8.1.1.6 Recommended Capacitor Types
        7. 8.1.1.7 Input and Output Capacitor Requirements (CIN and COUT)
        8. 8.1.1.8 Feed-Forward Capacitor (CFF)
        9. 8.1.1.9 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Circuit Soft-Start Control (NR/SS)
          1. 8.1.2.1.1 Inrush Current
        2. 8.1.2.2 Undervoltage Lockout (UVLO)
        3. 8.1.2.3 Power-Good (PG) Function
      3. 8.1.3 AC and Transient Performance
        1. 8.1.3.1 Power-Supply Rejection Ratio (PSRR)
        2. 8.1.3.2 Output Voltage Noise
        3. 8.1.3.3 Optimizing Noise and PSRR
          1. 8.1.3.3.1 Charge Pump Noise
        4. 8.1.3.4 Load Transient Response
      4. 8.1.4 DC Performance
        1. 8.1.4.1 Output Voltage Accuracy (VOUT)
        2. 8.1.4.2 Dropout Voltage (VDO)
          1. 8.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation
      5. 8.1.5 Sequencing Requirements
      6. 8.1.6 Negatively Biased Output
      7. 8.1.7 Reverse Current
      8. 8.1.8 Power Dissipation (PD)
        1. 8.1.8.1 Estimating Junction Temperature
        2. 8.1.8.2 Recommended Area for Continuous Operation (RACO)
    2. 8.2 Typical Applications
      1. 8.2.1 Low-Input, Low-Output (LILO) Voltage Conditions
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGR Package
20-Pin VQFN
Top View
TPS7A85A po_SBVS313.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
50mV 5 I ANY-OUT voltage setting pins. These pins connect to an internal feedback network. Connect these pins to ground, SNS, or leave floating. Connecting these pins to ground increases the output voltage, whereas connecting these pins to SNS increases the resolution of the ANY-OUT network but decreases the range of the network; multiple pins may be simultaneously connected to GND or SNS to select the desired output voltage. Leave these pins floating (open) when not in use. See ANY-OUT Programmable Output Voltage for additional details.
100mV 6
200mV 7
400mV 9
800mV 10
1.6V 11
BIAS 12 I BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions (that is, VIN = 1.2 V, VOUT = 1 V) to reduce power dissipation across the die. The use of a BIAS voltage improves dc and ac performance for VIN ≤ 2.2 V. A 10-µF capacitor (5-µF capacitance) or larger must be connected between this pin and ground if BIAS pin is used. If not used, this pin must be left floating or tied to ground and a capacitor is not required.
EN 14 I Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable functionality is not required, this pin must be connected to IN or BIAS.
FB 3 I Feedback pin connected to the error amplifier. Although not required, TI recommends a 10-nF feed-forward capacitor from FB to OUT (as close to the device as possible) to maximize ac performance. The use of a feed-forward capacitor may disrupt power-good (PG) functionality. See ANY-OUT Programmable Output Voltage and Adjustable Operation for more details.
GND 8, 18 — Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection.
IN 15, 16, 17 I Input supply voltage pin. A 10-μF or larger ceramic capacitor (5 μF of capacitance or greater) from IN to ground is required to reduce the impedance of the input supply. Place the input capacitor as close as possible to the input. See Input and Output Capacitor Requirements (CIN and COUT) for more details.
NR/SS 13 — Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference voltage noise and enables the soft-start function. Although not required, TI recommends a 10-nF or larger capacitor be connected from NR/SS to GND (as close as possible to the pin) to maximize ac performance. See Input and Output Capacitor Requirements (CIN and COUT) for more details.
OUT 1, 19, 20 O Regulated output pin. A 47-μF or larger ceramic capacitor (25 μF of capacitance or greater) from OUT to ground is required for stability and must be placed as close as possible to the output. Minimize the impedance from the OUT pin to the load. See Input and Output Capacitor Requirements (CIN and COUT) for more details.
PG 4 O Active-high, PG pin. An open-drain output indicates when the output voltage reaches VIT(PG) of the target. The use of a feed-forward capacitor may disrupt PG functionality. See Input and Output Capacitor Requirements (CIN and COUT) for more details.
SNS 2 I Output voltage sense input pin. This pin connects the internal R1 resistor to the output. Connect this pin to the load side of the output trace only if the ANY-OUT feature is used. If the ANY-OUT feature is not used, leave this pin floating. See ANY-OUT Programmable Output Voltage and Adjustable Operation for more details.
Thermal pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.