SBVS281A March   2016  – July 2016 TPS7A87

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation Features
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 System Start-Up Features
        1. 7.3.2.1 Programmable Soft-Start (NR/SSx)
        2. 7.3.2.2 Sequencing
          1. 7.3.2.2.1 Enable (ENx)
          2. 7.3.2.2.2 Undervoltage Lockout (UVLOx) Control
          3. 7.3.2.2.3 Active Discharge
        3. 7.3.2.3 Power-Good Output (PGx)
      3. 7.3.3 Internal Protection Features
        1. 7.3.3.1 Foldback Current Limit (ICLx)
        2. 7.3.3.2 Thermal Protection (Tsdx)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection
        1. 8.1.1.1 Setting the Output Voltage (Adjustable Operation)
        2. 8.1.1.2 Capacitor Recommendations
        3. 8.1.1.3 Input and Output Capacitor (CINx and COUTx)
        4. 8.1.1.4 Feed-Forward Capacitor (CFFx)
        5. 8.1.1.5 Noise-Reduction and Soft-Start Capacitor (CNR/SSx)
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Circuit Soft-Start Control (NR/SSx)
          1. 8.1.2.1.1 In-Rush Current
        2. 8.1.2.2 Undervoltage Lockout (UVLOx) Control
        3. 8.1.2.3 Power-Good (PGx) Function
      3. 8.1.3 AC and Transient Performance
        1. 8.1.3.1 Power-Supply Rejection Ratio (PSRR)
        2. 8.1.3.2 Channel-to-Channel Output Isolation and Crosstalk
        3. 8.1.3.3 Output Voltage Noise
        4. 8.1.3.4 Optimizing Noise and PSRR
          1. 8.1.3.4.1 Charge Pump Noise
        5. 8.1.3.5 Load Transient Response
      4. 8.1.4 DC Performance
        1. 8.1.4.1 Output Voltage Accuracy (VOUTx)
        2. 8.1.4.2 Dropout Voltage (VDO)
          1. 8.1.4.2.1 Behavior when Transitioning from Dropout into Regulation
      5. 8.1.5 Reverse Current Protection
      6. 8.1.6 Power Dissipation (PD)
        1. 8.1.6.1 Estimating Junction Temperature
        2. 8.1.6.2 Recommended Area for Continuous Operation (RACO)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 SPICE Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RTJ|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range and all voltages with respect to GND (unless otherwise noted)(1)
MIN MAX UNIT
Voltage INx, PGx, ENx(3) –0.3 7.0 V
INx, PGx, ENx (5% duty cycle, pulse duration = 200 µs) –0.3 7.5
OUTx –0.3 VINx + 0.3(2)
SS_CTRLx –0.3 VINx + 0.3(2)
NR/SSx, FBx(3) –0.3 3.6
Current OUTx(3) Internally limited A
PGx (sink current into device)(3) 5 mA
Temperature Operating junction, TJ –55 150 °C
Storage, Tstg –55 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The absolute maximum rating is VINx + 0.3 V or 7.0 V, whichever is smaller.
(3) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN MAX UNIT
VINx Input supply voltage range 1.4 6.5 V
VOUTx Output voltage range 0.8 – 1% 5.2 + 1% V
IOUTx Output current 0 500 mA
CINx Input capacitor, each input 10 µF
COUTx Output capacitor 10 µF
CNR/SSx Noise-reduction capacitor 1 µF
RPGx Power-good pullup resistance 10 100 kΩ
TJ Junction temperature range –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS7A87 UNIT
RTJ (WQFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 33 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 26.8 °C/W
RθJB Junction-to-board thermal resistance 8.0 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 8.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

over operating temperature range (TJ = –40°C to +125°C), VINx = 1.4 V or VOUTx(TARGET) + 0.2 V (whichever is greater), VOUTx(TARGET) = 0.8 V, IOUTx = 50 mA, VENx = 1.4 V, COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, SS_CTRLx = GND, PGx pin pulled up to VINx with 100 kΩ, and for each channel (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VINx(2) Input supply voltage range 1.4 6.5 V
VREF Reference voltage 0.8 V
VUVLOx Input supply UVLOx VINx rising 1.31 1.39 V
VUVLOx(HYS) VUVLOx hysteresis VINx falling hysteresis 290 mV
VOUTx Output voltage range 0.8 – 1% 5.2 + 1% V
VOUTx accuracy(1) 0.8 V ≤ VOUTx ≤ 5.2 V, 5 mA ≤ IOUTx ≤ 0.5 A –1.0% 1.0%
ΔVOUTx(ΔVINx) Line regulation IOUTx = 5 mA, 1.4 V ≤ VINx ≤ 6.5 V 0.003 %/V
ΔVOUTx(ΔIOUTx) Load regulation 5 mA ≤ IOUTx ≤ 0.5 A 0.03 %/A
VDO Dropout voltage 1.4 V ≤ VINx ≤ 5.3 V
IOUTx = 0.5 A, VFBx = 0.8 V – 3%		 100 mV
ILIM Output current limit VOUTx forced at 0.9 × VOUTx(TARGET), 0.8 1.1 1.5 A
IGND GND pin current Both channels enabled, per channel,
VINx = 6.5 V, IOUTx = 5 mA		 2.1 3.5 mA
Both channels enabled, per channel,
VINx = 1.4 V, IOUTx = 0.5 A		 4
ISDN Shutdown GND pin current Both channels shutdown, per channel, PGx = (open),
VINx = 6.5 V, VENx = 0.4 V		 0.1 15 μA
IENx ENx pin current VINx = 6.5 V, 0 V ≤ VENx ≤ 6.5 V –0.2 0.2 μA
VIL(ENx) ENx pin low-level input voltage (device disabled) 0 0.4 V
VIH(ENx) ENx pin high-level input voltage (device enabled) 1.1 6.5 V
ISS_CTRLx SS_CTRLx pin current VINx = 6.5 V, 0 V ≤ VSS_CTRLx ≤ 6.5 V –0.2 0.2 μA
VIT(PGx) PGx pin threshold For PGx transitioning low with falling VOUTx, expressed as a percentage of VOUTx(TARGET) 82% 88.9% 93%
Vhys(PGx) PGx pin hysteresis For PGx transitioning high with rising VOUTx, expressed as a percentage of VOUTx(TARGET) 1%
VOL(PGx) PGx pin low-level output voltage VOUTx < VIT(PGx), IPGx = –1 mA (current into device) 0.4 V
Ilkg(PGx) PGx pin leakage current VOUTx > VIT(PGx), VPGx = 6.5 V 1 µA
INR/SSx NR/SSx pin charging current VNR/SSx = GND, 1.4 V ≤ VINx ≤ 6.5 V,
VSS_CTRLx = GND		 4.0 6.2 9.0 µA
VNR/SSx = GND, 1.4 V ≤ VINx ≤ 6.5 V, VSS_CTRLx = VINx 65 100 150
IFBx FBx pin leakage current VINx = 6.5 V, VFBx = 0.8 V –100 100 nA
PSRR Power-supply rejection ratio f = 500 kHz, VINx = 3.8 V, VOUTx = 3.3 V,
IOUTx = 250 mA, CNR/SSx = 10 nF, CFFx = 10 nF		 40 dB
Vn Output noise voltage BW = 10 Hz to 100 kHz, VINx = 1.8 V, VOUTx = 0.8 V,
IOUTx = 0.5 A, CNR/SSx = 1 µF, CFFx = 100 nF		 3.8 μVRMS
Noise spectral density f = 10 kHz, VINx = 1.8 V, VOUTx = 0.8 V,
IOUTx = 0.5 A, CNR/SSx = 10 nF, CFFx = 10 nF		 11 nV/√Hz
Rdiss Output active discharge resistance VENx = GND 250 Ω
Tsdx Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140
(1) When the device is connected to external feedback resistors at the FBx pins, external resistor tolerances are not included.
(2) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2.

6.6 Typical Characteristics

at TJ = 25°C, 1.4 V ≤ VINx < 6.5 V, VINx ≥ VOUTx(TARGET) + 0.3 V, VOUTx = 0.8 V, SS_CTRLx = GND, IOUTx = 5 mA, VENx = 1.1 V, COUTx = 10 μF, CNR/SSx = 0 nF, CFFx = 0 nF, PGx pin pulled up to VOUTx with 100 kΩ, and SS_CTRLx = GND (unless otherwise noted)
TPS7A87 tc_PSRR_vs_Caps_5Vout.gif
IOUTx = 500 mA, VINx = 5.3 V
Figure 1. Power-Supply Rejection Ratio at VOUTx = 5.0 V
TPS7A87 tc_PSRR_vs_Vin.gif
VOUTx = 1.2 V, IOUTx = 500 mA, COUTx = 10 µF,
CNR/SSx = CFFx = 10 nF
Figure 3. Power-Supply Rejection Ratio vs
Frequency and Input Voltage
TPS7A87 tc_PSRR_vs_Cout_5Vout.gif
VOUTx = 5.0 V, VINx = 5.3 V, VENx = 1.7 V, IOUTx = 500 mA,
COUTx = ceramic, CFFx = 10 nF
Figure 5. Power-Supply Rejection Ratio vs
Frequency and Output Capacitance
TPS7A87 tc_Noise_Vs_Vout.gif
IOUTx = 500 mA
Figure 7. Output Noise vs Output Voltage
TPS7A87 D027_SBVS248.gif
VINx = VOUTx + 1.0 V, IOUTx = 500 mA, VRMS BW = 10 Hz to 100 kHz, COUTx = 10 µF, CNR/SSx = CFFx = 10 nF
Figure 9. Noise vs Frequency and Output Voltage
TPS7A87 D035_SBVS248.gif
VINx = 3.8 V, VOUTx = 3.3 V, IOUTx = 500 mA, VRMS BW = 10 Hz to 100 kHz, COUTx = 10 µF, CNR/SSx = 10 nF
Figure 11. Noise vs Frequency and CFFx
TPS7A87 D036_SBVS248.gif
VOUTx = 1.8 V, IOUTx = 500 mA, VRMS BW = 10 Hz to 100 kHz,
CFFx = 0.01 µF
Figure 13. Noise vs Frequency and COUTx
TPS7A87 D038_SBVS248.gif
VOUTx = 1.8 V, IOUTx = 500 mA, CNR/SSx = 1 µF,
BW = 10 Hz to 100 kHz
Figure 15. RMS Output Noise vs CFFx
TPS7A87 tc_Load_Trans_vs_Iout.gif
VINx = 5.3 V, COUTx = 10 µF, CFFx = CNR/SSx = 10 nF
Figure 17. Load Transient Response vs DC Load
TPS7A87 tc_Foldback.gif
VINx = 3.4 V, VOUTx = 3.3 V, 125°C curve truncated because of device entering thermal shutdown
Figure 19. Current Limit Foldback
TPS7A87 sbvs248_startup_01_GND.gif
VINx = 1.4 V
Figure 21. Start-Up (SS_CTRLx = GND, CNR/SSx = 10 nF)
TPS7A87 sbvs248_startup_1_VIN.gif
VINx = 1.4 V
Figure 23. Start-Up (SS_CTRLx = VINx, CNR/SSx = 1 µF)
TPS7A87 tc_Dropout_vs_Vin.gif
IOUTx = 500 mA
Figure 25. Dropout Voltage vs Input Voltage
TPS7A87 D008_SBVS248.gif
IOUTx = 50 mA
Figure 27. Line Regulation (VOUTx = 0.8 V)
TPS7A87 D009_SBVS248.gif
IOUTx = 5 mA
Figure 29. Line Regulation (VOUTx = 3.3 V)
TPS7A87 D005_SBVS248.gif
Both channels
Figure 31. Shutdown Current vs Input Voltage
TPS7A87 D004_SBVS248.gif
Both channels enabled
Figure 33. Ground Current vs Input Voltage
TPS7A87 D034_SBVS248.gif
Figure 35. PGx Low Level vs PGx Current (VINx = 6.5 V)
TPS7A87 D013_SBVS248.gif
VINx = VPGx = 6.5 V
Figure 37. PGx Leakage Current vs Temperature
TPS7A87 tc_Enable_Threshold.gif
Figure 39. Enable Threshold vs Temperature
TPS7A87 tc_PSRR_vs_Cnrss_5Vout.gif
VOUTx = 5 V, VINx = 5.3 V, VENx = 1.7 V, IOUTx = 500 mA,
COUTx = 10 µF, CFFx = 10 nF
Figure 2. Power-Supply Rejection Ratio vs
Frequency and CNR/SSx
TPS7A87 tc_PSRR_vs_Iout_1p2Vout.gif
VOUTx = 1.2 V, VINx = 1.4 V, VENx = 3.8 V, IOUTx = 500 mA,
COUTx = 10 µF, CNR/SSx = CFFx = 10 nF
Figure 4. Power-Supply Rejection Ratio vs
Frequency and Output Current
TPS7A87 D026_SBVS248.gif
VOUTx = 1.8 V, IOUTx = 100 mA, COUTx = 10 µF,
CNR/SSx = CFFx = 10 nF
Figure 6. Channel-to-Channel Output Voltage Isolation vs Frequency
TPS7A87 tc_Noise_5Vout.gif
IOUTx = 500 mA
Figure 8. Output Noise at VOUTx = 5 V
TPS7A87 D029_SBVS248.gif
VINx = 1.7 V, VOUTx = 1.2 V, IOUTx = 500 mA, VRMS BW = 10 Hz to 100 kHz, COUTx = 10 µF, CFFx = 10 nF
Figure 10. Noise vs Frequency and CNR/SSx
TPS7A87 D028_SBVS248.gif
VOUTx = 1.2 V, IOUTx = 500 mA, COUTx = 10 µF, CNR/SSx = 10 nF
Figure 12. Noise vs Frequency and VINx
TPS7A87 D037_SBVS248.gif
VOUTx = 1.8 V, IOUTx = 500 mA, CFFx = 0.01 µF,
BW = 10 Hz to 100 kHz
Figure 14. RMS Output Noise vs CNR/SSx
TPS7A87 tc_Load_Trans_vs_Vout.gif
VINx = VOUTx + 0.3 V, IOUTx = 10 mA to 500 mA, COUTx = 10 µF, CFFx = CNR/SSx = 10 nF
Figure 16. Load Transient Response vs VOUTx
TPS7A87 sbvs248_line_trans.gif
VINx = 1.4 V to 6.5 V to 1.4 V at 2 V/µs, VOUTx = 0.8 V,
IOUTx = 500 mA, CNR/SSx = CFFx = 10 nF
Figure 18. Line Transient
TPS7A87 sbvs248_startup_0_GNDr.gif
VINx = 1.4 V
Figure 20. Start-Up (SS_CTRLx = GND, CNR/SSx = 0 nF)
TPS7A87 sbvs248_startup_01_VIN.gif
VINx = 1.4 V
Figure 22. Start-Up (SS_CTRLx = VINx, CNR/SSx = 10 nF)
TPS7A87 tc_Dropout_vs_Iout.gif
Figure 24. Dropout Voltage vs Output Current
TPS7A87 tc_Load_Reg_1p2Vout.gif
Figure 26. Load Regulation (VOUTx = 1.2 V)
TPS7A87 tc_Load_Reg_3p3Vout.gif
VINx = 3.8 V
Figure 28. Load Regulation (VOUTx = 3.3 V)
TPS7A87 tc_Load_Reg_5Vout.gif
VINx = 5.5 V
Figure 30. Load Regulation (VOUTx = 5.0 V)
TPS7A87 tc_Ground_Pin_Current.gif
VINx = 1.4 V, both channels enabled
Figure 32. Ground Current vs Output Current
TPS7A87 D033_SBVS248.gif
Figure 34. PGx Low Level vs PGx Current (VINx = 1.4 V)
TPS7A87 tc_PG_Threshold.gif
Figure 36. PGx Threshold vs Temperature
TPS7A87 tc_NRSS_pin_current.gif
Figure 38. Soft-Start Current vs Temperature
(SS_CTRLx = GND)
TPS7A87 D015_SBVS248.gif
Figure 40. Input UVLOx Threshold vs Temperature