8.1.1.1 Setting the Output Voltage (Adjustable Operation)

Each LDO resistor feedback network sets the output voltage as (Figure 45 shows) with an output voltage range of 0.8 V to 5.15 V.

Figure 45. Adjustable Operation

Equation 1 relates the values R_1x and R_2x to V_OUTx(Target) and V_FBx. Equation 1 is a rearranged version of Equation 2 which simplifies the feedback resistor calculation. The current through the feedback network must be equal to or greater than 5 μA for optimum noise performance and accuracy, as shown in Equation 3.

The input bias current into the error amplifier (feedback pin current, I_FBx) and tighter tolerance resistors must be taken into account for optimizing the output voltage accuracy.

Table 4 lists the resistor combinations for several common output voltages using commercially-available, 1% tolerance resistors.

8.1.1.2 Capacitor Recommendations

The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output pins. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is not recommended because of large variations in capacitance.

Regardless of the selected ceramic capacitor type, ceramic capacitance varies with operating voltage and temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors recommended herein account for an effective capacitance derating of approximately 50%, but at higher V_INx and V_OUTx conditions (that is, V_INx = 5.5 V to V_OUTx = 5 V) the derating can be greater than 50% and must be taken into consideration.

8.1.1.3 Input and Output Capacitor (C_INx and C_OUTx)

The device is designed and characterized for operation with ceramic capacitors of 10 µF or greater (5 µF or greater of effective capacitance) at each input and output. Locate the input and output capacitors as near as practical to the respective input and output pins to minimize the trace inductance from the capacitor to the device.

8.1.1.4 Feedforward Capacitor (C_FFx)

Although a feedforward capacitor (C_FFx) from the FBx pin to the OUTx pin is not required to achieve stability, a 10-nF external C_FFx optimizes the transient, noise, and PSRR performance. A higher capacitance C_FFx can be used; however, the start-up time is longer and the power-good signal can incorrectly indicate that the output voltage is settled. The maximum recommended value is 100 nF.

To ensure proper PGx functionality, the time constant defined by C_NR/SSx must be greater than or equal to the time constant from C_FFx. For a detailed description, see Pros and Cons of Using a Feedforward Capacitor with a Low Dropout Regulator.

8.1.1.5 Noise-Reduction and Soft-Start Capacitor (C_NR/SSx)

Although a noise-reduction and soft-start capacitor (C_NR/SSx) from the NR/SSx pin to GND is not required, C_NR/SSx is highly recommended to control the start-up time and reduce the noise floor of the device. The typical value used is 10 nF, and the maximum recommended value is 10 µF.

8.1.2.1 Circuit Soft-Start Control (NR/SSx)

Each output of the device features a user-adjustable, monotonic, voltage-controlled soft start that is set with an external capacitor (C_NR/SSx). This soft start eliminates power-up initialization problems when powering field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled voltage ramp of the output also reduces peak in-rush current during start-up, which minimizes start-up transients to the input power bus.

The output voltage (V_OUTx) rises proportionally to V_NR/SSx during start-up as the LDO regulates so that the feedback voltage equals the NR/SSx voltage (V_FBx = V_NR/SSx). As such, the time required for V_NR/SSx to reach the nominal value determines the rise time of V_OUTx (start-up time).

The soft-start ramp time depends on the soft-start charging current (I_NR/SSx), the soft-start capacitance (C_NR/SSx), and the internal reference (V_REF). The approximate soft-start ramp time (t_SSx) can be calculated with Equation 4:

The SS_CTRLx pin for each output sets the value of the internal current source, maintaining a fast start-up time even with a large C_NR/SSx capacitor. When the SS_CTRLx pin is connected to GND, the typical value for the I_NR/SSx current is 6.2 µA. Connecting the SS_CTRLx pin to INx increases the typical soft-start charging current to 100 µA. The larger charging current for I_NR/SSx is useful when smaller start-up ramp times are required or when using larger noise-reduction capacitors.

Not using a noise-reduction capacitor on the NR/SSx pin and tying the SS_CTRLx pin to V_INx results in output voltage overshoot of approximately 10%. Connecting the SS_CTRLx pin to GND or using a capacitor on the NR/SSx pin minimizes the overshoot.

Values for the soft-start charging currents are provided in Electrical Characteristics.

8.1.2.1.1 In-Rush Current

In-rush current is defined as the current into the LDO at the INx pin during start-up. In-rush current then consists primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to measure because the input capacitor must be removed, which is not recommended. However, this soft-start current can be estimated by Equation 5:

Equation 5.

where

• V_OUTx(t) is the instantaneous output voltage of the turn-on ramp
• dV_OUTx(t) / dt is the slope of the V_OUTx ramp
• R_LOAD is the resistive load impedance

8.1.2.2 Undervoltage Lockout (UVLOx) Control

The UVLOx circuit ensures that the device stays disabled before the input or bias supplies reach the minimum operational voltage range and ensures that the device properly shuts down when the input supply collapses.

Figure 46 and Table 5 explain the UVLOx circuit response to various input voltage events, assuming V_ENx ≥ V_IH(ENx).

Figure 46. Typical UVLOx Operation

Similar to many other LDOs with this feature, the UVLOx circuit takes a few microseconds to fully assert. During this time, a downward line transient below approximately 0.8 V causes the UVLOx to assert for a short time; however, the UVLOx circuit does not have enough stored energy to fully discharge the internal circuits inside of the device. When the UVLOx circuit is not given enough time to fully discharge the internal nodes, the outputs are not fully disabled.

The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall time of the input supply when operating near the minimum V_INx.

8.1.2.3 Power-Good (PGx) Function

The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. The power-good circuit asserts whenever FBx, V_INx, or ENx are below the thresholds. The PGx operation versus the output voltage is shown in Figure 47, which Table 6 describes.

Figure 47. Typical PGx Operation

The PGx pin is open-drain and connecting a pullup resistor to an external supply enables other devices to receive power-good as a logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices.

To ensure proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and 100 kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and the upper limit of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup resistor is outside of this range, then the power-good signal may not read a valid digital logic level.

Using a large C_FFx with a small C_NR/SSx causes the power-good signal to incorrectly indicate that the output voltage has settled during turn-on. The C_FFx time constant must be greater than the soft-start time constant to ensure proper operation of the PGx during start-up. For a detailed description, see Pros and Cons of Using a Feedforward Capacitor with a Low Dropout Regulator.

The state of PGx is only valid when the device operates above the minimum supply voltage. During short brownout events and at light loads, power-good does not assert because the output voltage (therefore V_FBx) is sustained by the output capacitance.

8.1.3.1 Power-Supply Rejection Ratio (PSRR)

PSRR is a measure of how well the LDO control-loop rejects signals from V_INx to V_OUTx across the frequency spectrum (usually 10 Hz to 10 MHz). Equation 6 shows the PSRR calculation as a function of frequency for the input signal (V_INx[f]) and output signal (V_OUTx[f]).

Equation 6.

Even though PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for convenience.

A simplified diagram of PSRR versus frequency is shown in Figure 48.

Figure 48. Power-Supply Rejection Ratio Diagram

An LDO is often employed not only as a DC-DC regulator, but also to provide exceptionally clean power-supply voltages that exhibit ultra-low noise and ripple to sensitive system components. This usage is especially true for the TPS7A88-Q1.

The TPS7A88-Q1 features an innovative circuit to boost the PSRR between 200 kHz and 1 MHz; see Figure 4. To achieve the maximum benefit of this PSRR boost circuit, using a capacitor with a minimum impedance in the 100-kHz to 1-MHz band is recommended.

8.1.3.2 Channel-to-Channel Output Isolation and Crosstalk

Output isolation is a measure of how well the device prevents voltage disturbances on one output from affecting the other output. This attenuation appears in load transient tests on the other output; however, to numerically quantify the rejection, the output channel isolation is expressed in decibels (dB).

Output isolation performance is a strong function of the PCB layout. See Layout on how to optimize the isolation performance.

8.1.3.3 Output Voltage Noise

The TPS7A88-Q1 is designed for system applications where minimizing noise on the power-supply rail is critical to system performance. For example, the TPS7A88-Q1 can be used in a phase-locked loop (PLL)-based clocking circuit can be used for minimum phase noise, or in test and measurement systems where small power-supply noise fluctuations reduce system dynamic range.

LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions, thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower frequencies as a function of 1/f). Figure 49 shows a simplified output voltage noise density plot versus frequency.

Figure 49. Output Voltage Noise Diagram

For further details, see How to Measure LDO Noise.

8.1.3.4 Optimizing Noise and PSRR

The ultra-low noise floor and PSRR of the device can be improved in several ways, as Table 7 describes.

The noise-reduction capacitor (in conjunction with the noise-reduction resistor) forms a low-pass filter (LPF) that filters out the noise from the reference before gaining up with the error amplifier, which minimizes the output voltage noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with Equation 7. The typical value of R_NR is 250 kΩ. The effect of the C_NR/SSx capacitor increases when V_OUTx(Target) increases because the noise from the reference is gained up when the output voltage increases. For low-noise applications, a 10-nF to 10-µF C_NR/SSx is recommended.

The feedforward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feedforward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing out the loop bandwidth, thus improving mid-band PSRR.

A larger C_OUTx or multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing the high-frequency output impedance of the power supply.

Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the internal circuits. However, a high power dissipation across the die increases the output noise because of the increase in junction temperature.

Good PCB layout improves the PSRR and noise performance by providing heat sinking at low frequencies and isolating V_OUTx at high frequencies.

8.1.3.5 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby output voltage regulation is maintained. There are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure 50 are broken down in this section and are described in Table 8. Regions A, E, and H are where the output voltage is in steady-state.

Figure 50. Load Transient Waveform

The transient response peaks (V_OUTx(max) and V_OUTx(min)) are improved by using more output capacitance; however, doing so slows down the recovery time (W_rise and W_fall). Figure 51 shows these parameters during a load transient with a given pulse duration (PW) and current levels (I_OUTx(LO) and I_OUTx(HI)).

Figure 51. Simplified Load Transient Waveform

8.1.4.1 Output Voltage Accuracy (V_OUTx)

The device features an output voltage accuracy of 1% maximum that includes the errors introduced by the internal reference, load regulation, line regulation, and operating temperature as specified by Electrical Characteristics. Output voltage accuracy specifies minimum and maximum output voltage error relative to the expected nominal output voltage stated as a percent.

8.1.4.2 Dropout Voltage (V_DO)

Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and output voltage (V_DO = V_INx – V_OUTx) that is required for regulation. When V_INx drops below the required V_DO for the given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout voltage is proportional to the output current because the device is operating as a resistive switch, as shown in Figure 52.

Figure 52. Dropout Voltage versus Output Current

Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect to V_INx on this device because of the internal charge pump. Dropout voltage increases exponentially when the input voltage nears the maximum operating voltage because the charge pump multiplies the input voltage by a factor of 4 and then is internally clamped.

8.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation

Some applications can have transients that place the LDO into dropout, such as slower ramps on V_INX for start-up or load transients. As with other LDOs, the output can overshoot on recovery from these conditions.

A ramping input supply can cause an LDO to overshoot on start-up when the slew rate and voltage levels are in the right range, as shown in Figure 53. This condition is easily avoided by using an enable signal or increasing the soft-start time with C_SS/NRx.

Figure 53. Start-Up Into Dropout

8.1.6.1 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JT and Ψ_JB) are given in the table and are used in accordance with Equation 11.

Equation 11.

where

• P_D is the power dissipated as explained in Equation 8
• T_T is the temperature at the center-top of the device package, and
• T_B is the PCB surface temperature measured 1 mm from the device package and centered on the package edge

Table 9. Design Parameters