SBVS282 December   2016 TPS7A91

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage (VDO)
      3. 7.3.3 Output Voltage Accuracy
      4. 7.3.4 High Power-Supply Ripple Rejection (PSRR)
      5. 7.3.5 Low Output Noise
      6. 7.3.6 Output Soft-Start Control
      7. 7.3.7 Power-Good Function
      8. 7.3.8 Internal Protection Circuitry
        1. 7.3.8.1 Undervoltage Lockout (UVLO)
        2. 7.3.8.2 Internal Current Limit (ICL)
        3. 7.3.8.3 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Output
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Enable (EN) and Undervoltage Lockout (UVLO)
        2. 8.1.2.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
          1. 8.1.2.2.1 Noise Reduction
          2. 8.1.2.2.2 Soft-Start and Inrush Current
      3. 8.1.3 Capacitor Recommendation
        1. 8.1.3.1 Input and Output Capacitor Requirements (CIN and COUT)
          1. 8.1.3.1.1 Load-Step Transient Response
        2. 8.1.3.2 Feed-Forward Capacitor (CFF)
      4. 8.1.4 Power Dissipation (PD)
      5. 8.1.5 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 SPICE Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DSK Package
2.5-mm × 2.5-mm, 10-Pin SON
Top View

Pin Functions

PIN DESCRIPTION
NAME NO. I/O
EN 7 I Enable pin. This pin turns the LDO on and off. If VEN ≥ VIH(EN), the regulator is enabled. If VEN ≤ VIL(EN), the regulator is disabled. The EN pin must be connected to IN if the enable function is not used.
FB 3 I Feedback pin. This pin is the input to the control loop error amplifier and is used to set the output voltage of the device.
GND 4 — Device GND. Connect to the device thermal pad.
IN 9, 10 I Input pin. A 10 µF or greater input capacitor is required.
NR/SS 8 — Noise reduction pin. Connect this pin to an external capacitor to bypass the noise generated by the internal band-gap reference. The capacitor reduces the output noise to very low levels and sets the output ramp rate to limit inrush current.
OUT 1, 2 O Regulated output. A 10 µF or greater capacitor must be connected from this pin to GND for stability.
PG 5 O Open-drain power-good indicator pin for the LDO output voltage. A 10-kΩ to 100-kΩ external pullup resistor is required. This pin can be left floating or connected to GND if not used.
SS_CTRL 6 I Soft-start control pin. Connect this pin either to GND or IN to change the NR/SS capacitor charging current. If a CNR/SS capacitor is not used, SS_CTRL must be connected to GND to avoid output overshoot.
Thermal pad — Connect the thermal pad to the printed circuit board (PCB) ground plane, for an example layout see Figure 42.