SBVS282 December   2016 TPS7A91

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage (VDO)
      3. 7.3.3 Output Voltage Accuracy
      4. 7.3.4 High Power-Supply Ripple Rejection (PSRR)
      5. 7.3.5 Low Output Noise
      6. 7.3.6 Output Soft-Start Control
      7. 7.3.7 Power-Good Function
      8. 7.3.8 Internal Protection Circuitry
        1. 7.3.8.1 Undervoltage Lockout (UVLO)
        2. 7.3.8.2 Internal Current Limit (ICL)
        3. 7.3.8.3 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Output
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Enable (EN) and Undervoltage Lockout (UVLO)
        2. 8.1.2.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
          1. 8.1.2.2.1 Noise Reduction
          2. 8.1.2.2.2 Soft-Start and Inrush Current
      3. 8.1.3 Capacitor Recommendation
        1. 8.1.3.1 Input and Output Capacitor Requirements (CIN and COUT)
          1. 8.1.3.1.1 Load-Step Transient Response
        2. 8.1.3.2 Feed-Forward Capacitor (CFF)
      4. 8.1.4 Power Dissipation (PD)
      5. 8.1.5 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 SPICE Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range and all voltages with respect to GND (unless otherwise noted)(1)
MIN MAX UNIT
Voltage IN, PG, EN –0.3 7.0 V
IN, PG, EN (5% duty cycle, pulse duration ≤ 200 µs) –0.3 7.5
OUT –0.3 VIN + 0.3
SS_CTRL –0.3 VIN + 0.3
NR/SS, FB –0.3 3.6
Current OUT Internally limited A
PG (sink current into the device) 5 mA
Temperature Operating junction, TJ –55 150 °C
Storage, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Input supply voltage range 1.4 6.5 V
VOUT Output voltage range 0.8 5.2 V
IOUT Output current 0 1 A
CIN Input capacitor 10 µF
COUT Output capacitor 10 µF
CNR/SS Noise-reduction capacitor 0 10 µF
CFF Feedforward capacitor 0 100 nF
RPG Power-good pullup resistance 10 100 kΩ
TJ Junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS7A91 UNIT
DSK (SON)
10 PINS
RθJA Junction-to-ambient thermal resistance 56.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 46.3 °C/W
RθJB Junction-to-board thermal resistance 29.1 °C/W
ψJT Junction-to-top characterization parameter 0.8 °C/W
ψJB Junction-to-board characterization parameter 29.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating temperature range (TJ = –40°C to +125°C), 1.4 V ≤ VIN ≤ 6.5 V, VOUT(NOM) = 0.8 V, IOUT = 5 mA, VEN = 1.4 V, CIN = COUT = 10 μF, CNR/SS = CFF = 0 nF, SS_CTRL = GND, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input supply voltage range 1.4 6.5 V
VREF Reference voltage 0.8 V
VUVLO Input supply UVLO VIN rising 1.31 1.39 V
VHYS(UVLO) Input supply UVLO hysteresis  290 mV
VOUT Output voltage range 0.8 5.2 V
Output voltage accuracy(1) 1.4 V ≤ VIN ≤ 6.5 V, 5 mA ≤ IOUT ≤ 1 A –1.0% 1.0%
ΔVOUT(ΔVIN) Line regulation 0.005 %/V
ΔVOUT(ΔIOUT) Load regulation(2) 5 mA ≤ IOUT ≤ 1 A 0.02 %/A
VDO Dropout voltage VIN ≥ 1.4 V, IOUT = 1 A, VFB = 0.8 V – 3% 200 mV
ILIM Output current limit VOUT forced at 0.9 × VOUT(NOM),
VIN = VOUT(NOM) + 300 mV		 1.5 1.7 1.9 A
IGND GND pin current VIN = 6.5 V, IOUT = 5 mA 2.1 3.5 mA
VIN = 1.4 V, IOUT = 1 A 4
ISDN Shutdown GND pin current PG = (open), VIN = 6.5 V, VEN = 0.4 V 0.1 15 µA
IEN EN pin current VIN = 6.5 V, 0 V ≤ VEN ≤ 6.5 V –0.2 0.2 µA
VIL(EN) EN pin low-level input voltage (device disabled) 0 0.4 V
VIH(EN) EN pin high-level input voltage (device enabled) 1.1 6.5 V
ISS_CTRL SS_CTRL pin current VIN = 6.5 V, 0 V ≤ VSS_CTRL ≤ 6.5 V –0.2 0.2 µA
VIT(PG) PG pin threshold For PG transitioning low with falling VOUT, expressed as a percentage of VOUT(NOM) 82% 88.9% 93%
VHYS(PG) PG pin hysteresis For PG transitioning high with rising VOUT, expressed as a percentage of VOUT(NOM) 1%
VOL(PG) PG pin low-level output voltage VOUT < VIT(PG), IPG = –1 mA (current into device) 0.4 V
ILKG(PG) PG pin leakage current VOUT > VIT(PG), VPG = 6.5 V 1 µA
INR/SS NR/SS pin charging current VNR/SS = GND, VSS_CTRL = GND 4.0 6.2 9.0 µA
VNR/SS = GND, VSS_CTRL = VIN 65 100 150
IFB FB pin leakage current VIN = 6.5 V, VFB = 0.8 V –100 100 nA
PSRR Power-supply ripple rejection f = 500 kHz, VIN = 3.8 V, VOUT(NOM) = 3.3 V,
IOUT = 750mA, CNR/SS = 10 nF, CFF = 10 nF		 39 dB
Vn Output noise voltage BW = 10 Hz to 100 kHz, VIN = 1.8 V, VOUT(NOM) = 0.8 V,
IOUT = 1.0 A, CNR/SS = 10 nF, CFF = 10 nF		 4.7 µVRMS
Noise spectral density f = 10 kHz, VIN = 1.8 V, VOUT(NOM) = 0.8 V,
IOUT = 1.0 A, CNR/SS = 10 nF, CFF = 10 nF		 13 nV/√Hz
Rdiss Output active discharge resistance VEN = GND 250 Ω
Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140
(1) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
(2) The device is not tested under conditions where VIN > VOUT + 2.5 V and IOUT = 1 A because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.

6.6 Typical Characteristics

at TJ = 25°C, 1.4 V ≤ VIN ≤ 6.5 V, VIN ≥ VOUT(NOM) + 0.3 V, VOUT = 0.8 V, SS_CTRL = GND, IOUT = 5 mA, VEN = 1.1 V, COUT = 10 μF, CNR/SS = CFF = 0 nF, PG pin pulled up to VOUT with 100 kΩ, and SS_CTRL = GND (unless otherwise noted)
TPS7A91 tc_psrr_Vin_0.8.gif
VOUT = 0.8 V, IOUT = 1.0 A, COUT = 10 µF,
CNR/SS = CFF = 10 nF
Figure 1. PSRR vs Frequency and Input Voltage
TPS7A91 tc_psrr_vin_3.3V.gif
VOUT = 3.3 V, IOUT = 1.0 A, COUT = 10 µF,
CNR/SS = CFF = 10 nF
Figure 3. PSRR vs Frequency and Input Voltage
TPS7A91 tc_PSRR_vs_Iout_1.2V.gif
VOUT = 1.2 V, VIN = VEN = 1.7 V, COUT = 10 µF,
CNR/SS = CFF = 10 nF
Figure 5. PSRR vs Frequency and Output Current
TPS7A91 tc_psrr_cnr_1.2V.gif
VOUT = 1.2 V, VIN = VEN = 1.7 V, IOUT = 1.0 A, COUT = 10 µF,
CFF = 10 nF
Figure 7. PSRR vs Frequency and CNR/SS
TPS7A91 tc_noise_cnr.gif
VIN = 2.2 V, VOUT = 1.2 V, IOUT = 1.0 A, CIN = COUT = 10 µF,
CFF = 10 nF, VRMS BW = 10 Hz to 100 kHz
Figure 9. Spectral Noise Density vs Frequency and CNR/SS
TPS7A91 tc_noise_Cout.gif
VIN = 2.2 V, VOUT = 1.2 V, IOUT = 1.0 A, CIN = 10 µF,
CNR/SS = CFF = 10 nF, VRMS BW = 10 Hz to 100 kHz
Figure 11. Spectral Noise Density vs Frequency and COUT
TPS7A91 tc_Icl_temp.gif
VIN = 1.4 V, VOUT = 0.8 V
Figure 13. Current Limit vs Temperature
TPS7A91 tc_vdo_vs_vin.gif
IOUT = 1 A
Figure 15. Dropout Voltage vs Input Voltage
TPS7A91 tc_Vout_Vin.gif
IOUT = 50 mA
Figure 17. Line Regulation
TPS7A91 tc_Ignd_Iout.gif
VIN = 1.4 V
Figure 19. Ground Current vs Output Current
TPS7A91 tc_Vol_Ipg_1.5V.gif
Figure 21. PG Low Level Voltage vs PG Current
(VIN = 1.4 V)
TPS7A91 tc_PG_Temp.gif
Figure 23. PG Threshold vs Temperature
TPS7A91 tc_Inr_CNTRL_GND.gif
Figure 25. Soft-Start Current vs Temperature
(SS_CTRL = GND)
TPS7A91 tc_Ven_temp.gif
Figure 27. Enable Threshold vs Temperature
TPS7A91 tc_VOUTTrans1_2_sbvs282.gif
VIN = 1.5 V, IOUT = 100 mA to 1 A to 100 mA at 1 A/µs,
COUT = 10 µF, VPG = VOUT
Figure 29. Load Transient Response (VOUT = 1.2 V)
TPS7A91 tc_line_trans_sbvs282.gif
VIN = 1.4 V to 6.5 V to 1.4 V at 2 V/µs, VOUT = 0.8 V,
IOUT = 1 A, CNR/SS = CFF = 10 nF, VPG = VOUT
Figure 31. Line Transient
TPS7A91 tc_startup_01_GND_sbvs282.gif
VIN = 1.4 V, VPG = VOUT
Figure 33. Start-Up (SS_CTRL = GND, CNR/SS = 10 nF)
TPS7A91 tc_startup_1_VIN_sbvs282.gif
VIN = 1.4 V, VPG = VOUT
Figure 35. Start-Up (SS_CTRL = VIN, CNR/SS = 1 µF)
TPS7A91 tc_PSRR_vs_Vin_1.2V.gif
VOUT = 1.2 V, IOUT = 1.0 A, COUT = 10 µF,
CNR/SS = CFF = 10 nF
Figure 2. PSRR vs Frequency and Input Voltage
TPS7A91 tc_psrr_vin_5V.gif
VOUT = 5 V, IOUT = 1.0 A, COUT = 10 µF,
CNR/SS = CFF = 10 nF
Figure 4. PSRR vs Frequency and Input Voltage
TPS7A91 tc_PSRR_vs_Iout_3.3V.gif
A.
VOUT = 3.3 V, VIN = VEN = 3.8 V, COUT = 10 µF,
CNR/SS = CFF = 10 nF
Figure 6. PSRR vs Frequency and Output Current
TPS7A91 tc_noise_vout.gif
VIN = VOUT + 1.0 V, IOUT = 1.0 A, CIN = COUT = 10 µF,
CNR/SS = CFF = 10 nF, VRMS BW = 10 Hz to 100 kHz
Figure 8. Spectral Noise Density vs Frequency and
Output Voltage
TPS7A91 tc_noise_Cff.gif
VIN = 2.2 V, VOUT = 1.2 V, IOUT = 1.0 A, CIN = COUT = 10 µF, CNR/SS = 10 nF, VRMS BW = 10 Hz to 100 kHz
Figure 10. Spectral Noise Density vs Frequency and CFF
TPS7A91 tc_Icl_Vout.gif
VIN = 1.4 V, VOUT = 0.8 V
Figure 12. Current Limit Foldback
TPS7A91 tc_Vdo_vs_Iout.gif
VIN = 5.5 V
Figure 14. Dropout Voltage vs Output Current
TPS7A91 tc_Vout_Iout.gif
VIN = 1.4 V
Figure 16. Load Regulation
TPS7A91 tc_Isht_Vin.gif
VEN = 0.4 V
Figure 18. Shutdown Current vs Input Voltage
TPS7A91 tc_Ignd_Vin.gif
Figure 20. Ground Current vs Input Voltage
TPS7A91 tc_Vol_Ipg_6.5V.gif
Figure 22. PG Low Level Voltage vs PG Current
(VIN = 6.5 V)
TPS7A91 tc_PGlkg_Temp.gif
VIN = VPG = 6.5 V
Figure 24. PG Leakage Current vs Temperature
TPS7A91 tc_Inr_CNTRL_Vin.gif
Figure 26. Soft-Start Current vs Temperature
(SS_CTRL = VIN)
TPS7A91 tc_UVLO_temp.gif
Figure 28. Input UVLO Threshold vs Temperature
TPS7A91 tc_VOUTTrans5_0_sbvs282.gif
VIN = 5.5 V, IOUT = 100 mA to 1 A to 100 mA at 1 A/µs,
COUT = 10 µF, VPG = VOUT
Figure 30. Load Transient Response (VOUT = 5.0 V)
TPS7A91 tc_startup_0_GNDr_sbvs282.gif
VIN = 1.4 V, VPG = VOUT
Figure 32. Start-Up (SS_CTRL = GND, CNR/SS = 0 nF)
TPS7A91 tc_startup_01_VIN_sbvs282.gif
VIN = 1.4 V, VPG = VOUT
Figure 34. Start-Up (SS_CTRL = VIN, CNR/SS = 10 nF)