SLVSCP3C January   2015  – July 2016 TPS7B4253-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Short Circuit and Overcurrent Protection
      2. 7.3.2 Integrated Inductive Clamp Protection
      3. 7.3.3 OUT Short to Battery and Reverse Polarity Protection
      4. 7.3.4 Undervoltage Shutdown
      5. 7.3.5 Thermal Protection
      6. 7.3.6 Regulated Output (OUT)
      7. 7.3.7 Enable (EN)
      8. 7.3.8 Adjustable Output Voltage (FB and ADJ)
        1. 7.3.8.1 OUT Voltage Equal to the Reference Voltage
        2. 7.3.8.2 OUT Voltage Higher Than Reference Voltage
        3. 7.3.8.3 Output Voltage Lower Than Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 4 V
      2. 7.4.2 Operation With EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application With Output Voltage Equal to the Reference Voltage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input Capacitor
          2. 8.2.1.2.2 Output Capacitor
        3. 8.2.1.3 Application Curve
      2. 8.2.2 High-Side Switch Configuration
      3. 8.2.3 High Accuracy LDO
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation and Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DDA PowerPAD™ Package
8-Pin SO With External Thermal Pad
Top View
NC — No internal connection
PWP Package
20-Pin HTSSOP With Exposed Thermal Pad
Top View
NC — No internal connection

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME SO PowerPAD HTSSOP
ADJ 5 11 I Connect the reference to this pin. A low signal disables the device and a high signal enables the device. The reference voltage can be connected directly or by a voltage divider for lower output voltages. To compensate for line influences, connect a capacitor close to the device pins.
EN — 19 I This pin is the enable pin. The device goes to the STANDBY state when the enable pin goes lower than the threshold value.
FB 4 10 I This pin is the feedback pin which can connect to the external resistor divider to select the output voltage.
GND 3 6 G Ground reference
6 15
IN 8 20 I This pin is the device supply. To compensate for line influences, connect a capacitor close to the device pins.
NC 2 2 NC Not connected
3
4
5
7
8
9
7 12
13
14
16
17
18
OUT 1 1 O Block to GND with a capacitor close to the device pins with respect to the capacitance and ESR requirements listed in the Output Capacitor section.
Exposed thermal pad — Connect the thermal pad to the GND pin or leave it floating.
(1) I = input, O = output, G = ground, NC = no connect