SLVSDU9C February   2017  – December 2022

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Enable (EN)
      2. 7.3.2 Adjustable Power-Good Threshold (PG, PGADJ)
      3. 7.3.3 Adjustable Power-Good Delay Timer (DELAY)
      4. 7.3.4 Undervoltage Shutdown
      5. 7.3.5 Current Limit
      6. 7.3.6 Thermal Shutdown
      7. 7.3.7 Integrated Watchdog
        1. 7.3.7.1 Window Watchdog (WTS, ROSC, FSEL and WRS)
        2. 7.3.7.2 Standard Watchdog (WTS, ROSC and FSEL)
        3. 7.3.7.3 Watchdog Service Signal and Watchdog Fault Outputs (WD and WDO)
        4. 7.3.7.4 ROSC Status Detection (ROSC)
        5. 7.3.7.5 Watchdog Enable (PG and WD_EN)
        6. 7.3.7.6 Watchdog Initialization
        7. 7.3.7.7 Window Watchdog Operation (WTS = Low)
        8. 7.3.7.8 Standard Watchdog Operation (WTS = High)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With Input Voltage Lower Than 4 V
      2. 7.4.2 Operation With Input Voltage Higher Than 4 V
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
        3. 8.2.2.3 Power-Good Threshold
        4. 8.2.2.4 Power-Good Delay Period
        5. 8.2.2.5 Watchdog Setup
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

VI = 14 V, CO ≥ 4.7 µF, 1 mΩ < ESR < 20 Ω, and TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER-GOOD DELAY (DELAY)
t(DEGLITCH) Power-good deglitch time 50 180 250 µs
t(DLY_FIX) Fixed power-good delay No capacitor connect at DELAY pin 248 900 µs
t(DLY) Power-on-reset delay Delay capacitor value: C(DELAY) = 100 nF 20 ms
WATCHDOG (WD, WDO, WRS)
t(WD) Watchdog window duration R(ROSC) = 20 kΩ ±1%, FSEL = LOW 9 10 11 ms
R(ROSC) = 20 kΩ ±1%, FSEL = HIGH 45 50 55
t(WD_TOL) Tolerance of watchdog window duration using external resistor Excludes tolerance of R(ROSC) = 20 kΩ to 100 kΩ –10% 10%
tp(WD) Watchdog service-signal duration 100 µs
t(WD_HOLD) Watchdog output resetting time (percentage of settled watchdog window duration) 20 % of t(WD)
t(WD_RESET) Watchdog output resetting time R(ROSC) = 20 kΩ ± 1%, FSEL = LOW 1.8 2 2.2 ms
R(ROSC) = 20 kΩ ± 1%, FSEL = HIGH 9 10 11