SLVSCE8C January   2015  – September 2018 TPS7B7701-Q1 , TPS7B7702-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fault Detection and Protection
      2. 7.3.2  Short-Circuit and Overcurrent Protection
      3. 7.3.3  Short-to-Battery and Reverse Current Detection
      4. 7.3.4  Thermal Shutdown
      5. 7.3.5  Integrated Reverse-Polarity Protection
      6. 7.3.6  Integrated Inductive Clamp
      7. 7.3.7  Undervoltage Lockout
      8. 7.3.8  Enable (EN, EN1, and EN2)
      9. 7.3.9  Internal Voltage Regulator (VCC)
      10. 7.3.10 Current Sense Multiplexing
      11. 7.3.11 Adjustable Output Voltage (FB, FB1, and FB2)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With IN < 4.5 V
      2. 7.4.2 Operation With EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
        3. 8.2.2.3 Current Sense Resistor Selection
        4. 8.2.2.4 Current-Limit Resistor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT SENSE AND CURRENT-LIMIT
td(SENSE_SEL_r) Current-sense delay time from the rising edge of SENSE_SEL(1) V(ENx) ≥ 2 V, SENSE_EN = GND, SENSE_SEL rise from 0 to 5 V 10 µs
td(SENSE_SEL_f) Current-sense delay time from the falling edge of SENSE_SEL(1) V(ENx) ≥ 2 V, SENSE_EN = GND, SENSE_SEL fall from 5 to 0 V 10 µs
td(SENSE_EN_r) Current-sense delay time from rising edge of SENSE_EN(1) V(ENx) ≥ 2 V, SENSE_EN rise from 0 to 5 V 10 µs
td(SENSE_EN_f) Current-sense delay time from falling edge of SENSE_EN(1) V(ENx) ≥ 2 V, SENSE_EN fall from 5 to 0 V 10 µs
FAULT DETECTION
t(PD_RC) Reverse current (Short-to-BAT) shutdown deglitch time Delay to shut down the switch or LDO after a drop over ron becomes negative, I(OUTx) = –200 mA (typical), TA = 25°C 5 20 µs
t(BLK_RC) Reverse current blanking time Blanking time for reverse-current detection after power up, the rising edge of the ENx pin, or the current limiting event is over 16 ms
(1) Design information; specified by design; not production tested.