SBVS438 April   2024 TPS7B92

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Wide Supply Range
      2. 6.3.2 Low Quiescent Current
      3. 6.3.3 Dropout Voltage (VDO)
      4. 6.3.4 Current Limit
      5. 6.3.5 Leakage Null Control Circuit
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting VOUT for the TPS7B9201 Adjustable LDO
        2. 7.2.2.2 External Capacitor Requirements
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Power Dissipation
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Module
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.6 Power Dissipation (PD)

Circuit reliability requires consideration of the device power dissipation, circuit location on the printed circuit board (PCB), and correct sizing of the thermal plane. Make sure the PCB area around the regulator has few or no other heat-generating devices that cause added thermal stress.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD).

Equation 7. PD = (VIN – VOUT) × IOUT
Note: Power dissipation is minimized, and therefore greater efficiency achieved, by correct selection of the system voltage rails. For the lowest power dissipation, use the minimum input voltage required for correct output regulation.

For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. Make sure this pad area contains an array of plated vias that conduct heat to additional copper planes for increased heat dissipation.

The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to Equation 8, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA). The RθJA component is the combined PCB, device package, and the temperature of the ambient air (TA).

Equation 8. TJ = TA + (RθJA × PD)

The maximum peak power dissipation supported for the TPS7B92 is defined in the Absolute Maximum Ratings. The power dissipation ratings are recorded for the PCB configurations and are based on a JEDEC standard of 2s2p configuration (EIA/JESD51-x). The maximum supported power provides reliable operation for the TPS7B92. Exceeding the power limits leads to extreme junction temperatures (related to junction-to-ambient thermal resistance RθJA, Equation 8). Extreme temperatures risk damage to the device, and potentially reduces the expected device lifetime. Based on the safe operating limits, Figure 7-54 shows the supported load current (IOUT) for a headroom (VIN − VOUT).

GUID-20240317-SS0I-NRL2-P5FN-CP3TTVFF4KKK-low.svg
VIN − VOUT for safe operation
Figure 7-4 IOUT vs Headroom (VIN − VOUT)

Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design. Therefore, RθJA varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area. RθJA is used as a relative measure of package thermal performance. RθJA is improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimized. See the An empirical analysis of the impact of board layout on LDO thermal performance application note.