Brick-wall current limit, also known as constant current limit, is shown in Figure 8-3. In this mode, once I_PCL is reached and the current limit circuitry has time to respond, the TPS7H1121 LDO enters constant current regulation mode. In other words, the output voltage reduces to whatever value is needed to keep the output current at I_LIM. Once the fault is removed the device resumes regulation.

Due to the high power dissipation in brick-wall current limit, there is the possibility that the TPS7H1121 enters thermal shutdown which causes the device to stop regulation until the TPS7H1121 cools enough to exit thermal shutdown.

Figure 8-3 Simplified Brick-Wall Current Limit Waveforms

The programmable current limit's accuracy tightens with increased load current; Table 8-1 shows the recommended E96 value with a typical accuracy.

With the stipulated accuracy of the current limit, the programmable current limit resistor R_CL needs to be selected to accommodate the negative portion of the accuracy current limit circuitry. Additionally, a 20% headroom margin is recommended to prevent the current limit from intervening during nominal operation. For example an application with a nominal load of 1A can have a minimum programmable current limit setting of 1.4A / 97.6kΩ; the setting for a 97.6kΩ programmable current limit has a negative accuracy of -25% which leads a minimum intervening current limit of 1.05A.

For example an application with a nominal load of 1A is recommended to have a minimum intervening current of 1.2A; which yields a nominal current limit of 1.6A. Therefore an R_CL setting of 80.6kΩ with a negative accuracy of -25% leads to a minimum intervening current limit of 1.2A; which complies with the recommended 20% headroom.