SLVSH48A May   2024  – September 2024 TPS7H1121-SP

PRODMIX  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspections
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjustable Output Voltage (Feedback Circuit)
      2. 8.3.2  Enable
      3. 8.3.3  Dropout Voltage VDO
      4. 8.3.4  Output Voltage Accuracy
      5. 8.3.5  Output Noise
      6. 8.3.6  Power Supply Rejection Ratio (PSRR)
      7. 8.3.7  Soft Start
      8. 8.3.8  Power Good (PG)
      9. 8.3.9  Stability
        1. 8.3.9.1 Stability
        2. 8.3.9.2 STAB Pin
      10. 8.3.10 Programmable Current Limit
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable / Disable
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Configuration
        2. 9.2.2.2 Output Voltage Accuracy
        3. 9.2.2.3 Enable Threshold
        4. 9.2.2.4 Soft Start Capacitor
        5. 9.2.2.5 Programmable Current Limit Resistor
        6. 9.2.2.6 Characterization of Overcurrent Events that Exceed Thermal Limits
        7. 9.2.2.7 Power Good Pull Up Resistor
        8. 9.2.2.8 Capacitors
          1. 9.2.2.8.1 Hybrid Output Capacitor Network
        9. 9.2.2.9 Frequency Compensation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HFT|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Enable

When the enable pin is low, the device enters shutdown mode and does not regulate the output voltage. Normally, an external resistor divider from VIN to GND is used to feed EN.

Connection of the Enable pin directly to VIN is possible when VIN is below the Recommended Operating level of 7V; if a higher voltage level is to be provided to the Enable pin, then a simple voltage divider can be applied, refer to Equation 2 for resistor sizing guidance at the desired turn-on voltage.

Equation 2. VIN(rising) = VEN(rising) × (REN_TOP + REN_BOT) / REN_BOT

Similarly, a VIN(falling) voltage can also be calculated using Equation 3. The VIN(rising) and VIN(falling) can be thought of as configurable UVLO (under voltage-lockout) thresholds.

Equation 3. VIN(falling) = VEN(falling) × (REN_TOP + REN_BOT) / REN_BOT

While the TPS7H1121 will turn-on at a voltage of VEN of 0.6V (typ), it is recommended that the final value is above 0.8V. This is to ensure appropriate margin above the enable threshold during normal operation to prevent SEFIs during exposure to heavy ions. This recommendation is achieved by satisfying Equation 4.

Equation 4. VIN(final) × REN_BOT / (REN_TOP + REN_BOT) = VEN(final) > 0.8V

Alternatively, the EN pin can be driven directly from a micro-controller or FPGA. The low voltage threshold of the enable pin aids in support of 1.1V, 1.8V, 2.5V, and 3.3V logic levels. Similarly a final VEN above 0.8V for direct logic level driving is recommended (this is typically easily achieved with standard logic levels).