SLVSH46A July 2023 – October 2023 TPS7H2140-SEP
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The TPS7H2140-SEP can be configured in parallel operation either to increase the current capability, up to 5.4 A, or to reduce the RON (on-state resistance). Any channels combination can be parallel by connecting the desired channels outputs (OUTx) and enable (ENx) signals together. Figure 8-16 shows the input/output connections when paralleling all 4 channels of the TPS7H2140-SEP
For proper device operation follow the following recommendations:
Due to imbalance of currents in each channel (due to ΔRON) the total load current is not equally distributed. The channel current bounds are:
where N is equal to the # of parallel channels and ΔRON is the difference between the on-state resistance for any given channel.
At 25 °C the ΔRON maximum value is specified at 6 % (or 0.06), using this value and assuming the ILOAD is 5 A the current by each channel can be calculated (using Equation 13and Equation 14) as:
When paralleling channels is important to known that the current limit is programmed per channel based (or the same for all channels). The sensed current ratio on the current limit circuit have variations (as specified by dKCL/KCL). To deliver the expected load before reaching the current limit the designer most account for variation on the sensed current gain and variations on the channels currents due to on-resistance mismatch as described before. To select the current limit resistor when accounting for all system errors (ΔRON and dKCL/KCL) use:
As the sensed current is measured in a per channel based and reported on the CS pin. To measured the total load current of parallel channels, the individual current most be measured and added together. The individual currents are measured by using the SEH and SEL (mux inputs) in conjunction with the CS voltage.
The diagnostics as specified by Fault Table are globally reported, as the fault conditions affects all channels simultaneously. When using the internal clamp (VDS_CLAMP) to dissipate the inductive kick-back energy the energy most be limited to the maximum of a single channel.