SLVSH46A July   2023  – October 2023 TPS7H2140-SEP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Current and Voltage Conventions
      2. 8.3.2 Accurate Current Sense
      3. 8.3.3 Adjustable Current Limit
      4. 8.3.4 Inductive-Load Switching-Off Clamp
      5. 8.3.5 Fault Detection and Reporting
        1. 8.3.5.1 Diagnostic Enable Function
        2. 8.3.5.2 Multiplexing of Current Sense
        3. 8.3.5.3 Fault Table
        4. 8.3.5.4 FAULT Reporting
      6. 8.3.6 Full Diagnostics
        1. 8.3.6.1 Short-to-GND and Overload Detection
        2. 8.3.6.2 Open-Load Detection
          1. 8.3.6.2.1 Channel On
          2. 8.3.6.2.2 Channel Off
        3. 8.3.6.3 Short-to-Input Detection
        4. 8.3.6.4 Reverse Polarity Detection
        5. 8.3.6.5 Thermal Fault Detection
          1. 8.3.6.5.1 Thermal Shutdown
      7. 8.3.7 Full Protections
        1. 8.3.7.1 UVLO Protection
        2. 8.3.7.2 Loss-of-GND Protection
        3. 8.3.7.3 Protection for Loss of Power Supply
        4. 8.3.7.4 Reverse-Current Protection
        5. 8.3.7.5 MCU I/O Protection
      8. 8.3.8 Parallel Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
        1. 9.4.2.1 Without a GND Network
        2. 9.4.2.2 With a GND Network
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Parallel Operation

The TPS7H2140-SEP can be configured in parallel operation either to increase the current capability, up to 5.4 A, or to reduce the RON (on-state resistance). Any channels combination can be parallel by connecting the desired channels outputs (OUTx) and enable (ENx) signals together. Figure 8-16 shows the input/output connections when paralleling all 4 channels of the TPS7H2140-SEP

GUID-20230925-SS0I-ZMWN-ZQGB-HHRCB9M3CQ1N-low.svg Figure 8-16 Input and Output Connections when paralleling all channels in the TPS7H2140-SEP

For proper device operation follow the following recommendations:

  1. Connect the ENx inputs signals of the channels to be parallel together and as close to the device (I.C.) as possible.
  2. Connect the OUTx output signals of the channels to be parallel together and as close to the device (I.C.) as possible.
  3. Take in consideration the deviations (or errors) in the RON, current limit and voltage clamp for the system design.

Due to imbalance of currents in each channel (due to ΔRON) the total load current is not equally distributed. The channel current bounds are:

  • Equation 13. In(max)=ILOAD   N × 1+ RON1- RON
  • Equation 14. In(min)=ILOAD   N × 1- RON1+ RON

where N is equal to the # of parallel channels and ΔRON is the difference between the on-state resistance for any given channel.

At 25 °C the ΔRON maximum value is specified at 6 % (or 0.06), using this value and assuming the ILOAD is 5 A the current by each channel can be calculated (using Equation 13and Equation 14) as:

Equation 15. 1.11In 1.41

When paralleling channels is important to known that the current limit is programmed per channel based (or the same for all channels). The sensed current ratio on the current limit circuit have variations (as specified by dKCL/KCL). To deliver the expected load before reaching the current limit the designer most account for variation on the sensed current gain and variations on the channels currents due to on-resistance mismatch as described before. To select the current limit resistor when accounting for all system errors (ΔRON and dKCL/KCL) use:

Equation 16. RCL(max)=VCL_TH ×KCL 1-dKCLKCL In(max)

As the sensed current is measured in a per channel based and reported on the CS pin. To measured the total load current of parallel channels, the individual current most be measured and added together. The individual currents are measured by using the SEH and SEL (mux inputs) in conjunction with the CS voltage.

The diagnostics as specified by Fault Table are globally reported, as the fault conditions affects all channels simultaneously. When using the internal clamp (VDS_CLAMP) to dissipate the inductive kick-back energy the energy most be limited to the maximum of a single channel.

Note: The energy does not scale with the number of parallel channels and most be limited to the absolute maximum value of 40mJ.