SLVSH46A July   2023  – October 2023 TPS7H2140-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Current and Voltage Conventions
      2. 8.3.2 Accurate Current Sense
      3. 8.3.3 Adjustable Current Limit
      4. 8.3.4 Inductive-Load Switching-Off Clamp
      5. 8.3.5 Fault Detection and Reporting
        1. 8.3.5.1 Diagnostic Enable Function
        2. 8.3.5.2 Multiplexing of Current Sense
        3. 8.3.5.3 Fault Table
        4. 8.3.5.4 FAULT Reporting
      6. 8.3.6 Full Diagnostics
        1. 8.3.6.1 Short-to-GND and Overload Detection
        2. 8.3.6.2 Open-Load Detection
          1. 8.3.6.2.1 Channel On
          2. 8.3.6.2.2 Channel Off
        3. 8.3.6.3 Short-to-Input Detection
        4. 8.3.6.4 Reverse Polarity Detection
        5. 8.3.6.5 Thermal Fault Detection
          1. 8.3.6.5.1 Thermal Shutdown
      7. 8.3.7 Full Protections
        1. 8.3.7.1 UVLO Protection
        2. 8.3.7.2 Loss-of-GND Protection
        3. 8.3.7.3 Protection for Loss of Power Supply
        4. 8.3.7.4 Reverse-Current Protection
        5. 8.3.7.5 MCU I/O Protection
      8. 8.3.8 Parallel Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
        1. 9.4.2.1 Without a GND Network
        2. 9.4.2.2 With a GND Network
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over 4.5 V ≤ VIN ≤ 32 V, temperature range (−55°C ≤ TA ≤ 125°C), unless otherwise specified (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING VOLTAGE
INUVLOR Internal VIN UVLO rising 3.5 3.7 4 V
INUVLOF Internal VIN UVLO falling 3 3.2 3.4
HYSTIN-UVLO Internal VIN UVLO hysteresis 0.5
OPERATING CURRENT
IQ Quiescent current with diagnostics disabled ENx = 5 V, DIAG_EN = 0 V, IOUTx = 0 A, current limit = 2 A, all channels on 7.0 mA
IQ_DIAG Quiescent current with diagnostics enabled  ENx = DIAG_EN = 5 V, IOUTx = 0 A, current limit = 2 A, all channels on 6.2
ISD Shutdown current with diagnostics disabled  ENx = DIAG_EN  = OUTx = THER = 0 V
 		 TA=25°C 0.5 µA
TA=125°C 5
ISD_DIAG Shutdown current with diagnostic enabled  ENx = 0 V, DIAG_EN = 5 V, VIN – VOUTx < VOL_OFF, not in open-load mode 5 mA
tLOW_OFF ENx signal low time during cycling  ENx from high to low, if elapsed time > tLOW_OFF, the device enters into standby mode 10 12.5 15 ms
IF IN to OUTx forward leakage current  ENx = DIAG_EN = OUTx = 0 TA = 25°C 0.5 µA
 ENx = DIAG_EN = OUTx = 0 TA = 125°C 8
POWER STAGE
RON On-state resistance TA = 25°C 165 mΩ
TA = 125°C 280
ΔRON Percentage Difference in On-state resistance between channels (RON_CHx – RON_CHy )  TA = 25°C 6%
ICL_INTERNAL Internal current limit Internal current limit value, CL pin connected to GND 11 A
ICL_INTERNAL_TSD Current limit during thermal shutdown Internal current limit value under thermal shutdown 6.5
ICL_TSD Current limit during thermal shutdown External current limit value under thermal shutdown.
The percentage of the external current limit setting value		 70%
VDS_CLAMP Source-to-drain body diode voltage 50 70 V
OUTPUT DIODE CHARACTERISTICS
VF Drain−source diode voltage ENx = 0, IOUTX = −0.15 A. 0.3 0.7 0.9 V
IR1 Continuous reverse current from source to drain t < 60 s, VIN = 24 V, ENx = 0 V.
Single channel reversed current to supply		 TA = 25°C 2.5 A
IR2 Continuous reverse current from source to drain t < 60 s, VIN = 24 V, ENx = 0 V.
GND pin 1-kΩ resistor in parallel with diode.
Reverse-current condition, All channels reversed		 TA = 25°C 2.0
LOGIC INPUT (ENx, DIAG_EN, SEL, SEH, THER)
VIH Logic high-level voltage 2 V
VIL Logic low-level voltage 0.8
RPULL_DOWN Logic-pin pulldown resistor VIN = VDIAG_EN = 5 V 200 275 350 kΩ
VIN = VENx = VSEL = VSEH = VTHER = 5 V 100 175 250
DIAGNOSTICS
IGND_LOSS Output leakage current under GND loss condition 100 µA
VOL_OFF Open load detection threshold VENx = 0 V, when VIN – VOUTx > VOL_OFF.
 Duration longer than tOL_OFF, then open load is detected, off state.		 1.6 2.6 V
tOL_OFF Open-load detection threshold deglitch time VENx = 0 V, when VIN – VOUTx> VOL_OFF.
Duration longer than tOL_OFF, then open load is detected, off state		 300 550 800 µs
IOL_OFF Off-state output sink current VENx = 0 V, VDIAG_EN= 5 V, VIN – VOUTx = 24 V, open load TA = 125°C 100 µA
VOL_FAULT Fault low-output voltage IFAULT  = 2 mA 0.2 V
tCL_DEGLITCH Deglitch time when current limit occurs ENx = DIAG_EN = 5 V.
The deglitch time from current limit event to FAULT =  Low and VCS_FAULT		 220 µs
TSD Thermal shutdown threshold 160 175 °C
TSD_RST Thermal shutdown status reset threshold 155
Tsw Thermal swing shutdown threshold 60
THYS Hysteresis for resetting the thermal shutdown or thermal swing 10
CURRENT SENSE AND CURRENT LIMIT
KCS Current sense ratio  300
KCL Current limit ratio 2500
VCL_TH Current limit internal threshold voltage(3) 0.8 V
dKCS / KCS Current sense accuracy, (ICS × KCS – IOUT) / IOUT × 100 VIN = 13.5 V, IOUTx ≥ 5 mA  –65% 65%
dKCS / KCS VIN = 13.5 V, IOUTx ≥ 25 mA  –15% 15%
dKCS / KCS VIN = 13.5 V, IOUTx ≥ 50 mA  –8% 8%
dKCS / KCS VIN = 13.5 V, IOUTx ≥ 100 mA  –4% 4%
dKCL / KCL External current limit accuracy, (IOUTx – ICL × KCL) × 100 / (ICL × KCL) VIN = 13.5 V, ILIMIT ≥ 250 mA  –20% 20%
VIN = 13.5 V, 2 A ≤ ILIMIT ≤ 4 A –15% 15%
VCS_LINEAR Current-sense voltage linear range VIN ≥ 6.5 V 0 4 V
5 V ≤ VIN < 6.5 V 0 VIN – 2.5
IOUTx_LINEAR Output-current linear range VIN ≥ 6.5 V, VCS_LINEAR ≤ 4 V 0 2.5 A
5 V ≤ VIN < 6.5 V, VCS_LINEAR ≤ VIN – 2.5 V 0 2.5
VCS_FAULT Current sense pin output voltage VIN ≥ 7 V, FAULT mode 4.5 6.5 V
5 V ≤ VIN < 7 V, FAULT mode Min(VIN – 2.3, 4.5) 6.5
ICS_FAULT Current-sense pin output current available in fault mode VCS = 4.5 V, VIN > 7 V 15 mA
ICS_LEAK Current-sense leakage current in disabled mode VDIAG_EN = 0 V TA = 125ºC 0.5 µA
(1) All voltage values are with respect to GND.
(2) VCL_TH tolerance is included in the dKCL / KCL tolerance.