SLVSDO0F September   2018  – March 2024 TPS7H2201-SEP , TPS7H2201-SP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: All Devices
    6. 6.6  Electrical Characteristics: CFP and KGD Options
    7. 6.7  Electrical Characteristics: HTSSOP Option
    8. 6.8  Switching Characteristics (All Devices)
    9. 6.9  Quality Conformance Inspection
    10. 6.10 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable, Undervoltage, and Overvoltage Protection
      2. 8.3.2 Adjustable Rise Time
      3. 8.3.3 Programmable Current Limiting
      4. 8.3.4 Programmable Fault Timer
      5. 8.3.5 Current Sense
      6. 8.3.6 Parallel Operation
      7. 8.3.7 Reverse Current Protection
      8. 8.3.8 Forward Leakage Current
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Redundancy
      2. 9.2.2 Protection
      3. 9.2.3 Design Requirements
      4. 9.2.4 Detailed Design Procedure
        1. 9.2.4.1 Undervoltage Lockout
        2. 9.2.4.2 Overvoltage Protection
        3. 9.2.4.3 Current Limit
        4. 9.2.4.4 Programmable Fault Timers
        5. 9.2.4.5 Soft Start Time
      5. 9.2.5 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DAP|32
  • KGD|0
  • HKR|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Programmable Fault Timer

A capacitor connected from the ILTIMER pin to GND determines the programmable current limit fault time duration. The ILTIMER pin will charge the capacitor to 0.5 V during an overload condition and will discharge it otherwise through an internal pull down resistance. The time that the device will be in current limit before turning off is configured by CILTIMER and the time can be calculated using Equation 9. Connecting this pin to VIN will cause the device to be disabled once the internal current limit timer expires as shown in Figure 7-5. However, connecting it to GND will disable the internal timer functionality completely and therefore, in the case of a short, the device will remain at the programmed current limit indefinitely. When using the internal timer, the programmable current limit may not have time to settle to its programmed value. Because of this, the programmable current limit could briefly fall outside of its defined accuracy threshold. The fast trip off current limit, however, will remain valid.

Equation 9. GUID-7A88531E-8486-4CD2-AD6B-2BD88CBA3168-low.gif

The time that the device remains disabled after the current limit timer expires is configurable through a capacitor connected from the RTIMER pin to GND. The RTIMER pin will charge the capacitor to 0.5 V after the switch is turned off and will discharge it otherwise. The time can be calculated using Equation 9. Connecting this pin to GND will keep the device disabled and it will require the device to be enabled by cycling the EN pin (Refer to EN Signal Low Time to Restart Device (tLOW)). The behavior of the ILTIMER and RTIMER pins for a soft short, hard short and internal timer conditions are shown in Figure 8-2, Figure 8-3, and Figure 8-4, respectively. Please notice that Figure 8-2 and Figure 8-3 assume the fault is not present after the switch has been disabled and enabled again (retry mode). If the fault is present after the retry mode, the device will go into current limit mode and this cycle will repeat until the fault is no longer present.

Table 8-1 and Table 8-2 summarizes the fault duration time and retry time based on the pin conditions.

Table 8-1 Fault Time Duration for ILTIMER Pin Conditions
ILTIMER Pin Condition Fault Time Duration During Overload
VIN 15 μs (typ), 35 μs (max)
GND Indefinitely
Capacitor to GND (CILTIMER) Equation 9
Float Not valid (do not float pin)

Table 8-2 Time to Retry During an Overload Condition for RTIMER Pin Conditions
RTIMER Pin Condition Time to Retry During an Overload
GND Disabled (switch off) until EN is low for t > tLOW (20 μs)
Capacitor to GND (CRTIMER) Equation 9
Float Not valid (do not float pin)
GUID-20230411-SS0I-LRS2-XLMC-5RJPFSCS0VV9-low.svg Figure 8-2 Soft Short Programmable Fault Timer Operation Connecting Capacitors to ILTIMER and RTIMER Pins
GUID-20230411-SS0I-NC7T-MLBD-NX3FPRN9HTLR-low.svg Figure 8-3 Hard Short Programmable Fault Timer Operation Connecting Capacitors to ILTIMER and RTIMER Pins
GUID-20230411-SS0I-KV5M-2FVM-QDBK0DGJLP4K-low.svg Figure 8-4 Programmable Fault Timer Operation Using the Internal Current Limit Timer and Disabling the Retry Mode

The programmable fault timers, ILTIMER and RTIMER, should be set in such a way that the capacitor for one timer is discharged before the other timer expires to ensure proper operation. In the specific case of using the internal ILTIMER, the RTIMER capacitor should be sized such that it is discharged before the internal ILTIMER expires, assuming the fault is still present. Figure 8-5 shows a situation where this constraint is not met as the RTIMER is much larger than the ILTIMER and therefore, the CRTIMER is not discharged before the CILTIMER reaches 0.5 V, which is when the ILTIMER will expire. In order to avoid this situation, the constraint shown in Equation 10 must be met. Using this equation, once a capacitor for a timer has been selected (C1 in Equation 10), the maximum value for the capacitor of the second timer can be determined. The internal pull-down resistance for each of the timers can be found in the Electrical Characteristics: All Devices table. For the situation shown in Figure 8-5, C1 and RPD1 in Equation 10 correspond to the RTIMER.

GUID-20230411-SS0I-N9XT-35TZ-GX7VR22WZ3LD-low.svg Figure 8-5 Programmable Fault Timer Capacitors Constraint
Equation 10. GUID-86A1DD2D-7345-4390-AB62-586C94D0E82B-low.gif