SLVSDO0F September   2018  – March 2024 TPS7H2201-SEP , TPS7H2201-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: All Devices
    6. 6.6  Electrical Characteristics: CFP and KGD Options
    7. 6.7  Electrical Characteristics: HTSSOP Option
    8. 6.8  Switching Characteristics (All Devices)
    9. 6.9  Quality Conformance Inspection
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable, Undervoltage, and Overvoltage Protection
      2. 8.3.2 Adjustable Rise Time
      3. 8.3.3 Programmable Current Limiting
      4. 8.3.4 Programmable Fault Timer
      5. 8.3.5 Current Sense
      6. 8.3.6 Parallel Operation
      7. 8.3.7 Reverse Current Protection
      8. 8.3.8 Forward Leakage Current
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Redundancy
      2. 9.2.2 Protection
      3. 9.2.3 Design Requirements
      4. 9.2.4 Detailed Design Procedure
        1. 9.2.4.1 Undervoltage Lockout
        2. 9.2.4.2 Overvoltage Protection
        3. 9.2.4.3 Current Limit
        4. 9.2.4.4 Programmable Fault Timers
        5. 9.2.4.5 Soft Start Time
      5. 9.2.5 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DAP|32
  • KGD|0
  • HKR|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics: All Devices

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT
POWER SUPPLIES AND CURRENTS
VINHUVLO Internal VIN UVLO voltage, rising 1.32 V
VINLUVLO Internal VIN UVLO voltage, falling 1.23 V
HYSTVIN-UVLO Internal VIN UVLO hysteresis 92 mV
IQ Quiescent current IOUT = 0 mA,
VIN = EN = 5 V, CS resistor of 20 kΩ to GND		 1, 2, 3 2.4 6.5 mA
IF VIN to VOUT forward leakage current EN = VOUT = GND, measured VOUT current 1.5 V ≤ VIN ≤ 7 V 1, 2, 3 250 µA
 VIN =1.5 V 1, 2, 3 3.27
VIN = 1.8 V 1, 2, 3 3.35
VIN= 3.3 V 1, 2, 3 3.62
VIN = 5 V 1, 2, 3 4.11
VIN = 7 V 1, 2, 3 6.82
ISD VIN VIN off-state supply current EN = GND,
IOUT = 0 mA, measured VIN current		 VIN = 5 V 1, 2, 3 0.4 3 mA
VIN = 3.3 V 1, 2, 3 0.3 3
VIN = 1.8 V 1, 2, 3 0.2 3
After TID = 100 krad, VIN = 1.8, 3.3, and 5 V 1 3.1
SOFT START
ISS Soft start charge current 1 V on SS pin 1, 2, 3 65 83 µA
SRSS Soft start slew rate SS pin floating, COUT = 10 µF 295 mV/µs
ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT
VIHEN EN/UVLO threshold voltage, rising 1, 2, 3 0.56 0.61 0.65 V
VILEN EN/UVLO threshold voltage, falling 1, 2, 3 0.47 0.51 0.55 V
HYSTEN EN/UVLO hysteresis voltage 1, 2, 3 93 124 mV
tLOW EN signal low time during cycling RTIMER = GND, IL = 1 A, IVOUT = 2 A See Figure 7-1 9, 10, 11 20 µs
VINEN VIN percentage for enable(2) 4, 5, 6 75%
IEN EN pin input leakage current EN = VIN = 5 V 1, 2, 3 12 nA
OVERVOLTAGE PROTECTION (OVP)
VOVPR OVPR thresold voltage, rising 1, 2, 3 0.52 0.57 0.63 V
VOVPF OVPF threshold voltage, falling 1, 2, 3 0.5 0.55 0.59 V
HYSTOVP OVP hysteresis voltage 1.6 V < VIN < 7 V 1, 2, 3 20 55 mV
IOVP OVP pin input leakage current 1, 2, 3 15 nA
CURRENT LIMIT AND CURRENT SENSE
tCSEN Time for valid CS output after enable CSS = 120 nF 9, 10, 11 5 ms
Minimum VOUT current for valid CS output 1, 2, 3 750 mA
VOUT current change to CS change delay time 0.5-A rising step, 100 mA/µs, 1.5 V ≤ VIN ≤ 7 V 9, 10, 11 16 74 µs
VOUT current change to CS change delay time 0.5-A falling step, 100 mA/µs, 1.5 V ≤ VIN ≤ 7 V 9, 10, 11 16 73 µs
CS pin accuracy 0.75 A ≤ IVOUT ≤ 7.5 A 4, 5, 6 –10% 10%
CS pin voltage 0.75 A ≤ IVOUT ≤ 7.5 A, no OCP 1, 2, 3 VIN – 0.4 V
Current limit setting, IIL IVOUT ≤ 1 A 1, 2, 3 IVOUT + 0.5 A
1A < IVOUT ≤ 3 A 1, 2, 3 IVOUT + 1
IVOUT > 3 A 1, 2, 3 IVOUT + 1.5
Programmable current limit accuracy 1.5 V ≤ VIN ≤ 7 V 4, 5, 6 –20% 20%
Fast trip off current limit VIN = 5 V, 10-mΩ short in 10 µs 22 A
TIMERS
IILTIMER ILTIMER charge current 1, 2, 3 0.7 1 1.38 µA
PDILTIMER ILTIMER internal pull-down resistance 40 mV on ILTIMER pin 1, 2, 3 38 153 Ω
IRTIMER RTIMER charge current 1, 2, 3 0.7 1 1.38 µA
PDRTIMER RTIMER internal pull-down resistance 40 mV on RTIMER pin 1, 2, 3 38 153 Ω
THERMAL SHUTDOWN
Thermal shutdown VIN = 5 V 175 °C
Thermal shutdown hysteresis VIN = 5 V 20 °C
(1) For subgroup definitions, see Quality Conformance Inspection table.
(2) VIN must be ≥ 75% of its final value before EN is asserted only if VINSR > VOUTSR.