SLVSGX6B February   2023  – December 2023 TPS7H3302-SEP , TPS7H3302-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VTT Sink and Source Regulator
      2. 7.3.2 Reference Input (VDDQSNS)
      3. 7.3.3 Reference Output (VTTREF)
      4. 7.3.4 EN Control (EN)
      5. 7.3.5 Power-Good Function (PGOOD)
      6. 7.3.6 VTT Current Protection
      7. 7.3.7 VIN UVLO Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 VTT Output Capacitor
        4. 8.2.2.4 VTTSNS Connection
        5. 8.2.2.5 Low VDD Applications
        6. 8.2.2.6 S3 and Pseudo-S5 Support
        7. 8.2.2.7 Tracking Startup and Shutdown
        8. 8.2.2.8 Output Tolerance Consideration for VTT DIMM or Module Applications
        9. 8.2.2.9 LDO Design Guidelines
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DAP|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over 2.375 ≤ VDD ≤ 3.5 V, VLDOIN = 1.8 V, VDDQSNS = 1.8 V, EN = VDD, TA = – 55°C to 125°C; Standard DDR Application; all voltages with respect to AGND, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVDD Quiescent current EN = 3.3 V, no load 18 30 mA
IVDD(SHDN) Shutdown current EN = 0 V, no load VDDQSNS = 0 V 1.75 3 mA
VDDQSNS > 0.78 V 5 6
IVLDOIN Quiescent current of VLDOIN EN = 3.3 V, no load 450 1200 µA
IVLDOIN(SHDN) Shutdown current of VLDOIN EN = 0 V, no load 0.5 1 µA
IVDDQSNS VDDQSNS input current EN = 3.3 V 4 6 µA
VTT OUTPUT
VTTSNS Output DC voltage, VTT IVTT = 5 mA VDDQSNS = VLDOIN = 2.5 V (DDR1) 1.24 1.25 1.26 V
VDDQSNS = VLDOIN = 1.8V (DDR2) 0.89 0.9 0.91
VDDQSNS = VLDOIN = 1.5 V (DDR3) 0.745 0.752 0.759
VDDQSNS = VLDOIN = 1.35 V (DDR3L) 0.67 0.677 0.684
VDDQSNS = VLDOIN = 1.2 V (DDR4) 0.596 0.602 0.608
IVTT = –5 mA VDDQSNS = VLDOIN = 2.5 V (DDR1) 1.25 1.26 1.27 V
VDDQSNS = VLDOIN = 1.8V (DDR2) 0.9 0.91 0.92
VDDQSNS = VLDOIN = 1.5 V (DDR3) 0.752 0.76 0.768
VDDQSNS = VLDOIN = 1.35 V (DDR3L) 0.675 0.685 0.692
VDDQSNS = VLDOIN = 1.2 V (DDR4) 0.602 0.61 0.618
–1 A ≤ IVTT ≤ 1 A VDDQSNS = VLDOIN = 2.5 V (DDR1) 1.24 1.26 1.28 V
VDDQSNS = VLDOIN = 1.8V (DDR2) 0.885 0.910 0.93
VDDQSNS = VLDOIN = 1.5 V (DDR3) 0.735 0.76 0.78
VDDQSNS = VLDOIN = 1.35 V (DDR3L) 0.66 0.69 0.72
VDDQSNS = VLDOIN = 1.2 V (DDR4) 0.585 0.6 0.63
VDO Dropout voltage,
VDO = VLDOIN – VTTREF
VDO recorded when VTT – VTTREF = 50 mV		 VDDQSNS = 2.5 V (DDR1) IVTT = 0.5 A 5 60 mV
IVTT = 1 A 60 180
IVTT = 2 A 190 465
VDDQSNS = 1.8 V (DDR2) IVTT = 0.5 A 8 70
IVTT = 1 A 65 200
IVTT = 2 A 190 475
VDDQSNS = 1.5 V (DDR3) IVTT = 0.5 A 5 65
IVTT = 1 A 60 180
IVTT = 2 A 180 420
VDDQSNS = 1.35 V (DDR3L) IVTT = 0.5 A 4 60
IVTT = 1 A 60 180
IVTT = 2 A 175 420
VDDQSNS = 1.2 V (DDR4) IVTT = 0.5 A 4 60
IVTT = 1 A 60 180
IVTT = 2 A 175 420
VTT(TOL) VTT Tolerance to VTTREF (VTT – VTTREF) IVTT = -3 A 1 18 30 mV
IVTT = 3 A -30 -15 -1
ILIM_SRC_VTT VTT sourcing current limit Ramp output 0 A to 10 A, record current when VTT reaches lowest value 5 9 A
ILIM_SNK_VTT VTT sinking current limit Ramp output 0 A to -10 A, record current when VTT reaches highest value 5 10 A
RDSCHRG VTT discharge resistance VDDQSNS = 0 V, VTT = 0.3 V, EN = 0 V 7 25 Ω
POWER GOOD
VPG(LOW, Falling) VTT PGOOD threshold with respect to VTTREF    PGOOD window lower falling threshold -21% -20% -18%
VPG(LOW, Rising) PGOOD window lower rising threshold -17% -15% -13%
VPG(HI, Falling) VTT PGOOD threshold with respect to VTTREF PGOOD window High falling threshold 13% 15% 17%
VPG(HI, Rising) PGOOD window High rising threshold 18% 20% 21%

VPG(HYST)
 
VTT PGOOD hysteresis

 5%
tPG(delay) PGOOD startup delay Startup rising edge, VTTSNS within 20% of VTTREF 4 ms
tPG_BAD(delay) PGOOD bad delay VTTSNS outside of the ±20% PGOOD window 1.95 µs
VPG(OL) Power good output low IPGOOD(SINK) = 4 mA 0.4 V
IPG(LKG) Power good leakage VTTSNS = VTTREF (PGOOD high impedance), PGOOD = VDD + 0.2 V 0.07 1 µA
VDDQSNS AND VTTREF
VDDQSNSUVLO VDDQSNS UVLO turn-on threshold VDDQSNS rising 750 900 mV
VDDQSNSUVLO(HYST) VDDQSNS UVLO hysteresis 75 150
VTTREF VTTREF voltage VDDQSNS / 2 V
VTTREF VTTREF voltage tolerance to VDDQSNS -10 mA ≤ IVTTREF ≤ 10 mA VDDQSNS = 2.5 V 49% 51%
VDDQSNS = 1.8 V 49% 51%
VDDQSNS = 1.5 V 49%             51.25%
VDDQSNS = 1.35 V 49% 51.5%
VDDQSNS = 1.2 V 49% 51.5%
-3 mA ≤ IVTTREF ≤ 3 mA VDDQSNS = 1.5 V 49% 51%
VDDQSNS = 1.35 V 49% 51%
VDDQSNS = 1.2 V 49% 51%
ILIM_SRC_VTTREF VTTREF sourcing current limit Sourcing current ramped from 0 to 55mA.  Find when VTTREF drops to half its original value 35 45 mA
ILIM_SNK_VTTREF VTTREF sinking current limit Sinking current ramped from 0 to 16.5mA.  Find when VTTREF hits peak value 12 15
IVTTREF(dis) VTTREF discharge current EN = 0 V, VDDQSNS = 0 V, VTTREF = 0.5 V 1.3 mA
UVLO AND ENABLE
VDDUVLO VDD UVLO turn-on threshold 2.18 2.3 V
VDDUVLO(HYST) VDD UVLO hysteresis 40 mV
VIH_EN Enable high-level input voltage (turn-on) 1.7 V
VIL_EN Enable low-level input voltage (turn-off) 0.3 V
VEN(HYS) Enable hysteresis voltage 700 mV
IEN(LKG) Enable input leakage current -1 1 µA