SLVSGX6B February   2023  – December 2023 TPS7H3302-SEP , TPS7H3302-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VTT Sink and Source Regulator
      2. 7.3.2 Reference Input (VDDQSNS)
      3. 7.3.3 Reference Output (VTTREF)
      4. 7.3.4 EN Control (EN)
      5. 7.3.5 Power-Good Function (PGOOD)
      6. 7.3.6 VTT Current Protection
      7. 7.3.7 VIN UVLO Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 VTT Output Capacitor
        4. 8.2.2.4 VTTSNS Connection
        5. 8.2.2.5 Low VDD Applications
        6. 8.2.2.6 S3 and Pseudo-S5 Support
        7. 8.2.2.7 Tracking Startup and Shutdown
        8. 8.2.2.8 Output Tolerance Consideration for VTT DIMM or Module Applications
        9. 8.2.2.9 LDO Design Guidelines
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DAP|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20220602-SS0I-ZSGV-MXZR-4SLJ6NGGVKGS-low.png Figure 5-1 DAP Package, 32-Pin HTSSOP (Top View)
Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
VTTREF 4 O Reference output. Connect to GND through 0.1-µF ceramic capacitor.
VDDQSNS 5 I VDDQ sense input. Reference input for VTTREF.(2)
VLDOIN 7 I Supply voltage for the LDO. Connect to VDDQ voltage or an alternate voltage source.
8
PGND 9 — Power ground. Connect to system ground.
10
11
EN 20 I Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device.
VDD 21 I 2.5- or 3.3-V power supply. A ceramic decoupling capacitor with a value between 1 and 10 µF is required.
PGOOD 22 O PGOOD output pin. PGOOD pin is an open drain output to indicate the output voltage is within specification.
VTT 23 O Power output for VTT LDO.
24
25
26
AGND 28 — Signal ground. Connect to system ground.
VTTSNS 29 I Voltage sense for VTT. Place capacitor close to pin. Route sense line to VTT near load.
NC 1-3, 6, 12-19, 27, 30-32 — No connect. These pins are not internally connected. It is recommended to connect these pins to ground to prevent charge buildup; however, these pins can also be left open or tied to any voltage between ground and VDD.
Thermal Pad — Connect to PGND. This is internally floating.
(1) I = Input, O = Output, — = Other
(2) VDDQSNS shall be connected to the regulated voltage supplying VDDQ. If the VDDQ supply is also used for VLDOIN, an RC filter is recommended to isolate transients from VLDOIN to VDDQ.