SLVSEN7D april   2019  – may 2023 TPS7H4001-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - All Devices
    6. 7.6  Electrical Characteristics: CDFP and KGD Options
    7. 7.7  Electrical Characteristics: HTSSOP (SHP) Option
    8. 7.8  Electrical Characteristics: HTSSOP (QMLP) Option
    9. 7.9  Quality Conformance Inspection
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Adjusting the Output Voltage
      4. 8.3.4  Safe Start-Up Into Prebiased Outputs
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Enable and Adjust UVLO
      7. 8.3.7  Adjustable Switching Frequency and Synchronization (SYNC)
        1. 8.3.7.1 Internal Oscillator Mode
        2. 8.3.7.2 External Synchronization Mode
        3. 8.3.7.3 Primary-Secondary Operation Mode
      8. 8.3.8  Soft-Start (SS/TR)
      9. 8.3.9  Power Good (PWRGD)
      10. 8.3.10 Sequencing
      11. 8.3.11 Output Overvoltage Protection (OVP)
      12. 8.3.12 Overcurrent Protection
        1. 8.3.12.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.12.2 Low-Side MOSFET Overcurrent Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Turn-On Behavior
      15. 8.3.15 Slope Compensation
        1. 8.3.15.1 Slope Compensation Requirements
      16. 8.3.16 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Soft-Start Capacitor Selection
        6. 9.2.2.6 Undervoltage Lockout (UVLO) Set Point
        7. 9.2.2.7 Output Voltage Feedback Resistor Selection
          1. 9.2.2.7.1 Minimum Output Voltage
        8. 9.2.2.8 Compensation Component Selection
      3. 9.2.3 Parallel Operation
      4. 9.2.4 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDW|44
  • KGD|0
  • HKY|34
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.10 Sequencing

Many of the common power-supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins.

The sequential method is shown in Figure 8-7 using two TPS7H4001-SP devices. The PWRGD pin of the first device is coupled to the EN pin of the second device, which enables the second power supply after the primary supply reaches regulation.

GUID-CFC0DFDC-5947-4B5A-BAE9-83B279416028-low.gif Figure 8-7 Sequential Start-Up Sequence

Figure 8-8 shows the method implementing ratiometric sequencing by connecting the SS/TR pins of two devices together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start time, the pullup current source must be doubled in Equation 5 as there is only one SS/TR capacitor. A similar situation applies if a resistor divider is used in the EN pin, that is, only one resistor divider is needed and the factor of 2 must be taken into account when calculating the resistor values. This ratiometric connection is the one used in primary mode as described in the Adjustable Switching Frequency and Synchronization (SYNC) section.

GUID-95028459-5CAE-4BC8-B596-8094389D8E55-low.gif Figure 8-8 Ratiometric Start-Up Sequence

Ratiometric and simultaneous power-supply sequencing can be implemented by connecting the resistor network of R1 and R2 (shown in Figure 8-9) to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the VOUT2 slightly before, after, or at the same time as VOUT1. Equation 8 is the voltage difference between VOUT1 and VOUT2.

To design a ratiometric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2 reaches regulation, use a negative number in Equation 6 and Equation 7 for ΔV. Equation 8 results in a positive number for applications where the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.

The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (VSS-OFFSET = 30 mV) in the soft-start circuit and the offset created by the pullup current source (ISS = 2.5 μA) and tracking resistors, the VSS-OFFSET and ISS are included as variables in the equations.

To ensure proper operation of the device, the calculated R1 value from Equation 6 must be greater than the value calculated in Equation 9.

Equation 6. GUID-85DF1283-2398-4C19-B15E-1A5F72183221-low.gif
Equation 7. GUID-011526C1-FB34-4731-A741-09D47EC3AE43-low.gif
Equation 8. GUID-3927558F-BFD8-4B0F-9D9A-0160069B4229-low.gif
Equation 9. GUID-C0E66E40-47EA-4C73-8132-277638EAE7B8-low.gif
GUID-BBFC3B1C-3E43-47D3-9B3A-47C70759DE67-low.gif Figure 8-9 Ratiometric and Simultaneous Start-Up Sequence