SLVSEN7D april   2019  – may 2023 TPS7H4001-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - All Devices
    6. 7.6  Electrical Characteristics: CDFP and KGD Options
    7. 7.7  Electrical Characteristics: HTSSOP (SHP) Option
    8. 7.8  Electrical Characteristics: HTSSOP (QMLP) Option
    9. 7.9  Quality Conformance Inspection
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Adjusting the Output Voltage
      4. 8.3.4  Safe Start-Up Into Prebiased Outputs
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Enable and Adjust UVLO
      7. 8.3.7  Adjustable Switching Frequency and Synchronization (SYNC)
        1. 8.3.7.1 Internal Oscillator Mode
        2. 8.3.7.2 External Synchronization Mode
        3. 8.3.7.3 Primary-Secondary Operation Mode
      8. 8.3.8  Soft-Start (SS/TR)
      9. 8.3.9  Power Good (PWRGD)
      10. 8.3.10 Sequencing
      11. 8.3.11 Output Overvoltage Protection (OVP)
      12. 8.3.12 Overcurrent Protection
        1. 8.3.12.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.12.2 Low-Side MOSFET Overcurrent Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Turn-On Behavior
      15. 8.3.15 Slope Compensation
        1. 8.3.15.1 Slope Compensation Requirements
      16. 8.3.16 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Soft-Start Capacitor Selection
        6. 9.2.2.6 Undervoltage Lockout (UVLO) Set Point
        7. 9.2.2.7 Output Voltage Feedback Resistor Selection
          1. 9.2.2.7.1 Minimum Output Voltage
        8. 9.2.2.8 Compensation Component Selection
      3. 9.2.3 Parallel Operation
      4. 9.2.4 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDW|44
  • KGD|0
  • HKY|34
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics - All Devices

TJ = –55°C to 125°C, VIN = PVIN = 3 V to 7 V (unless otherwise noted)
PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN AND PVIN PINS)
PVIN operating input voltage 1, 2, 3 3.0 7.0 V
PVIN internal UVLO threshold PVIN rising 1, 2, 3 2.425 2.50 2.575 V
PVIN internal UVLO hysteresis Load = 0 A 1, 2, 3 425 450 475 mV
VIN operating input voltage 1, 2, 3 3.0 7.0 V
VIN internal UVLO threshold VIN rising 1, 2, 3 2.71 2.75 2.80 V
VIN internal UVLO hysteresis 1, 2, 3 134 150 178 mV
VIN shutdown supply current VEN = 0 V 1, 2, 3 2.32 2.85 mA
VIN operating – non switching supply current VSENSE = VBG 1, 2, 3 4 6 mA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising 1, 2, 3 1.110 1.14 1.172 V
Falling 1, 2, 3 1.080 1.11 1.148
Input current VEN = 1.1 V 1, 2, 3 4.8 6.1 7.6 µA
Hysteresis current VEN = 1.3 V 1, 2, 3 2.4 3.0 3.9 µA
ERROR AMPLIFIER
Error amplifier input offset voltage VSENSE = 0.6 V 1, 2, 3 –2 2.55 mV
VSENSE pin input current VSENSE = 0.6 V 1, 2, 3 –15 15 nA
Error amplifier transconductance (gm) –2 μA < ICOMP < 2 μA, V(COMP) = 1 V 9, 10, 11 1150 1800 2400 µS
Error amplifier DC gain(2) VSENSE = 0.6 V 10000 V/V
Error amplifier source V(COMP) = 1 V, 100-mV input overdrive 1, 2, 3 100 140 190 µA
Error amplifier sink V(COMP) = 1 V, 100-mV input overdrive 1, 2, 3 100 140 190 µA
Error amplifier output resistance 7 MΩ
COMP to Iswitch gm(3) COMP = 0.5 V –55℃ 3 28 38 49 S
25℃ 1 29 40 50
125℃ 2 30 41 52
SLOPE COMPENSATION
Slope compensation(4) fSW = 100 kHz, RSC = 1.1 MΩ –1.2 A/µs
fSW = 500 kHz, RSC = 196 kΩ –6.0
fSW = 1000 kHz, RSC = 80.6 kΩ –16.0
THERMAL SHUTDOWN
Thermal shutdown 190 °C
Thermal shutdown hysteresis 18 °C
INTERNAL SWITCHING FREQUENCY
Internally set frequency RT = Open VIN = 3 V 4, 5, 6 444 473 515 kHz
VIN = 5 V 4, 5, 6 449 502  560
Externally set frequency RT = 1.07 MΩ (1%) VIN = 3 V 4, 5, 6 80 98 125 kHz
VIN = 5 V 4, 5, 6 80 100 125
RT = 165 kΩ (1%) VIN = 3 V 4, 5, 6 455 495 535
VIN = 5 V 4, 5, 6 475 523 615
RT = 73.2 kΩ (1%) VIN = 3 V 4, 5, 6 689 850 1011
VIN = 5 V 4, 5, 6 760 986 1212
VIN = 5 V, TID = 100 krad(Si) 4 760 1145 1425
EXTERNAL SYNCHRONIZATION
SYNC1/SYNC2 out low-to-high rise time (10%/90%) Cload = 25 pF 9, 10, 11 70 180 ns
SYNC1/SYNC2 out high-to-low fall time (90%/10%) Cload = 25 pF 9, 10, 11 10 21 ns
SYNC2 to SYNC1 rising edge phase shift 9, 10, 11 77 85 94 °
SYNC1 falling edge delay(3) 9, 10, 11 165 180 185 °
SYNC1/SYNC2 out high level threshold IOH = 50 µA 1, 2, 3 VIN – 0.3 V
SYNC1/SYNC2 out low level threshold IOL = 50 µA 1, 2, 3 600 mV
SYNC1/SYNC2 in low level threshold PVIN = VIN = 3 V 1, 2, 3 800 mV
PVIN = VIN = 5 V 800
PVIN = VIN = 7 V(3) 800
SYNC1/SYNC2 in high level threshold PVIN = VIN = 3 V 1, 2, 3 2.25 V
PVIN = VIN = 5 V 3.5
PVIN = VIN = 7 V(3) 4.9
SYNC1 in frequency range PVIN = VIN = 5 V 4, 5, 6  100 1000 kHz
SYNC1 in duty cycle range Duty cycle of external clock 4, 5, 6 40 60 %
PH (PH PIN)
Minimum on time Measured at 10% to 90% of VIN,
IPH = 2 A, VIN = 3 V		 9, 10, 11 190 235 ns
Measured at 10% to 90% of VIN,
IPH = 2 A, VIN = 5 V		 9, 10, 11 190 225
SOFT START AND TRACKING (SS/TR PIN)
SS charge current 1, 2, 3 1.5 2.5 3 µA
SS/TR to VSENSE matching(3) V(SS/TR) = 0.3 V 1, 2, 3 30 90 mV
POWER GOOD (PWRGD PIN)
VSENSE threshold VSENSE falling (fault) 1, 2, 3 90 91 %VREF
VSENSE rising (good) 94 97
VSENSE rising (fault) 109 111
VSENSE falling (good) 103 106
Output high leakage VSENSE = VREF, V(PWRGD) = 5 V 1, 2, 3 30 181 nA
Output low I(PWRGD) = 2 mA 1, 2, 3 0.3 V
Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 μA 1, 2, 3 0.6 1 V
Minimum SS/TR voltage for PWRGD 1, 2, 3 1.1 V
(1) For subgroup definitions, see Quality Conformance Inspection table.
(2) Ensured by design only. Not tested in production.
(3) Bench verified. Not tested in production.
(4) Example values are shown in the table.  Actual values are application specific and should be calculated as detailed in the Slope Compensation section.