There are several considerations in determining the value of the output capacitor. The selection of the output capacitor is driven by both the desired output voltage ripple, and the allowable voltage deviation due to a large, abrupt change in load current (load step). For space applications, the value of capacitance also has to account for the mitigation of single event effects (SEE). The output capacitance needs to be selected based on the more stringent of these three criteria. When selecting the capacitors, care should be taken to select capacitors with a sufficient voltage rating, temperature rating, and consideration of any effective capacitance changes due to DC bias effects. It is also important to note that the value of the output capacitor directly influences the modulator pole of the converter frequency response, as described in Section 9.2.2.10.

The first criteria to consider is the desired response to a load step. This generally occurs when the regulator is temporarily not able to supply sufficient output current during a large, fast increase in the current needs of the load. This may occur during a transition from no load to full load, or when powering an FPGA with large current swings. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. Equation 14 shows the minimum output capacitance, from the electrical point of view, necessary to accomplish this.

Where ΔI_OUT is the change in output current, f_SW is the regulator switching frequency, and ΔVOUT is the allowable change in the output voltage. For this example, the transient load response is specified as a 2.5% change in VOUT for a load step of 12A. This results in a minimum capacitance of 582μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. However, for space applications and large capacitance values, tantalum capacitors are typically used, which have a certain ESR value to take into consideration.

The next criteria is to calculate the required capacitance to meet the output voltage ripple requirements using Equation 15 where VOUT_{ripple(desired)} is the maximum allowable output voltage ripple, and ∆I_L is the inductor ripple current. In this case, the maximum desired output voltage ripple is 20mV, and the inductor ripple current is 2.2A. Under these conditions, a minimum capacitance value of 28µF is calculated.

Finally, the ESR of the capacitor must be considered when meeting the output voltage ripple requirements using Equation 16. It is determined that an ESR value of 9mΩ or less is required.

Additional capacitance deratings for aging, temperature, and DC bias should be factored in, which increases the minimum required output capacitance value. Additionally, capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. The selected bank of output capacitors must handle the ripple current calculated in Equation 11.

For this specific design, taking into consideration all of the above requirements, 3x330µF T530 Tantalum capacitors are selected with a resulting combined ESR of 1.9mΩ at the 500kHz switching frequency. Additionally, a 22µF and 1µF ceramic capacitor are added in parallel for high frequency filtering. This results in a total capacitance of 1.013mF.

Equation 17 can be used as an approximation to calculate the resulting output voltage ripple when considering both the capacitance and ESR. For this design, the resulting output ripple estimation is 4.7mV.