SNVS983A April   2024  – August 2024 TPS7H4011-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Remote Sensing and Setting VOUT
        1. 8.3.3.1 Minimum Output Voltage
        2. 8.3.3.2 Maximum Output Voltage
      4. 8.3.4  Enable
      5. 8.3.5  Fault Input (FAULT)
      6. 8.3.6  Power Good (PWRGD)
      7. 8.3.7  Adjustable Switching Frequency and Synchronization
        1. 8.3.7.1 Internal Clock Mode
        2. 8.3.7.2 External Clock Mode
        3. 8.3.7.3 Primary-Secondary Synchronization
      8. 8.3.8  Turn-On Behavior
        1. 8.3.8.1 Soft-Start (SS_TR)
        2. 8.3.8.2 Safe Start-Up Into Prebiased Outputs
        3. 8.3.8.3 Tracking and Sequencing
      9. 8.3.9  Protection Modes
        1. 8.3.9.1 Overcurrent Protection
          1. 8.3.9.1.1 High-Side 1 Overcurrent Protection (HS1)
          2. 8.3.9.1.2 High-Side 2 Overcurrent Protection (HS2)
          3. 8.3.9.1.3 COMP Shutdown
          4. 8.3.9.1.4 Low-Side Overcurrent Sinking Protection
        2. 8.3.9.2 Output Overvoltage Protection (OVP)
        3. 8.3.9.3 Thermal Shutdown
      10. 8.3.10 Error Amplifier and Loop Response
        1. 8.3.10.1 Error Amplifier
        2. 8.3.10.2 Power Stage Transconductance
        3. 8.3.10.3 Slope Compensation
        4. 8.3.10.4 Frequency Compensation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Operating Frequency
        2. 9.2.2.2  Output Inductor Selection
        3. 9.2.2.3  Output Capacitor Selection
        4. 9.2.2.4  Input Capacitor Selection
        5. 9.2.2.5  Soft-Start Capacitor Selection
        6. 9.2.2.6  Rising VIN Set Point (Configurable UVLO)
        7. 9.2.2.7  Output Voltage Feedback Resistor Selection
        8. 9.2.2.8  Output Voltage Accuracy
        9. 9.2.2.9  Slope Compensation Requirements
        10. 9.2.2.10 Compensation Component Selection
        11. 9.2.2.11 Schottky Diode
      3. 9.2.3 Application Curve
      4. 9.2.4 Parallel Operation Compensation
      5. 9.2.5 Inverting Buck-Boost
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HLB|30
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.8 Output Voltage Accuracy

To determine the output voltage DC accuracy, the following sources of error are considered:

  • VREF within the Electrical Characteristics table is the predominant source of error. This encompasses the error due to the reference voltage and error amplifier offset. The across temperature minimum of 0.595V, maximum of 0.603V, and typical of 0.6V results in an accuracy of –0.83% and +0.5%. If this error is instead centered around an average reference voltage of 0.599V, the accuracy is calculated as ±0.67%.
  • The VREF specification in not measured in a switching, closed-loop configuration. Figure 6-32 can be used to see the effects of output current (load regulation) and switching. However, it is seen that across the complete 12A load, there is only a +155µV and –43µV deviation. This deviation is considered small enough such that load regulation is not included in this accuracy calculation. Additionally, since a differential remote sense connection is provided, it is possible to regulate the voltage directly across the load, which compensates for load regulation error due to ground offsets.
  • The external error due to the resistor tolerance of the RFB_TOP and RFB_BOT resistors need to be added. Since it is assumed the error is uncorrelated, it is decided to add the errors as a sum of squares. For the selected 0.1% tolerance RFB_TOP and RFB_BOT resistors, the total error is R(error) = sqrt(0.1%2 + 0.1%2 ) = ±0.14%.

Equation 20 is used to calculate the system error for output voltage accuracy.

Equation 20. System(error) = VREF(error) + RFB(error)

The negative system error calculation is System(error) = –0.83% – 0.14% = –0.97% and the positive system error is System(error) = 0.5% + 0.14% = 0.64%. Therefore, the total system error is calculated to be +0.64%/–0.97%. If the total system error is centered, this comes to ±0.81%. These each meet the ±1% accuracy target.

Lifetime drift data could similarly be added. Group C data may be used to aid in this calculation. For this example, it is assumed the lifetime drift is minimal compared to the other sources of error and it is therefore not added.