SNVS983A April   2024  – August 2024 TPS7H4011-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Remote Sensing and Setting VOUT
        1. 8.3.3.1 Minimum Output Voltage
        2. 8.3.3.2 Maximum Output Voltage
      4. 8.3.4  Enable
      5. 8.3.5  Fault Input (FAULT)
      6. 8.3.6  Power Good (PWRGD)
      7. 8.3.7  Adjustable Switching Frequency and Synchronization
        1. 8.3.7.1 Internal Clock Mode
        2. 8.3.7.2 External Clock Mode
        3. 8.3.7.3 Primary-Secondary Synchronization
      8. 8.3.8  Turn-On Behavior
        1. 8.3.8.1 Soft-Start (SS_TR)
        2. 8.3.8.2 Safe Start-Up Into Prebiased Outputs
        3. 8.3.8.3 Tracking and Sequencing
      9. 8.3.9  Protection Modes
        1. 8.3.9.1 Overcurrent Protection
          1. 8.3.9.1.1 High-Side 1 Overcurrent Protection (HS1)
          2. 8.3.9.1.2 High-Side 2 Overcurrent Protection (HS2)
          3. 8.3.9.1.3 COMP Shutdown
          4. 8.3.9.1.4 Low-Side Overcurrent Sinking Protection
        2. 8.3.9.2 Output Overvoltage Protection (OVP)
        3. 8.3.9.3 Thermal Shutdown
      10. 8.3.10 Error Amplifier and Loop Response
        1. 8.3.10.1 Error Amplifier
        2. 8.3.10.2 Power Stage Transconductance
        3. 8.3.10.3 Slope Compensation
        4. 8.3.10.4 Frequency Compensation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Operating Frequency
        2. 9.2.2.2  Output Inductor Selection
        3. 9.2.2.3  Output Capacitor Selection
        4. 9.2.2.4  Input Capacitor Selection
        5. 9.2.2.5  Soft-Start Capacitor Selection
        6. 9.2.2.6  Rising VIN Set Point (Configurable UVLO)
        7. 9.2.2.7  Output Voltage Feedback Resistor Selection
        8. 9.2.2.8  Output Voltage Accuracy
        9. 9.2.2.9  Slope Compensation Requirements
        10. 9.2.2.10 Compensation Component Selection
        11. 9.2.2.11 Schottky Diode
      3. 9.2.3 Application Curve
      4. 9.2.4 Parallel Operation Compensation
      5. 9.2.5 Inverting Buck-Boost
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HLB|30
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.7.3 Primary-Secondary Synchronization

Primary-secondary device synchronization is a system level configuration that makes use of a primary device in internal clock mode and one to three secondary devices in external synchronization mode. Therefore, this configuration allows paralleling up to four devices in quadrature (90° out of phase with each other) in order to obtain increased current output with minimized voltage ripple.

The primary device is configured in internal oscillator mode by setting SYNCM = GND and the desired frequency programmed by using the RT pin as described in Section 8.3.7.1. The secondary devices are configured by setting SYNCM = AVDD. Therefore, the primary SYNC1 and SYNC2 output clock signals, in combination with the secondary device SYNC2 states, can be used to connect two, three, or four devices in parallel. Under this configuration, two devices can be programed 180° out of phase or four devices can be programmed 90° out of phase (three devices will result in two device pairs 90° out of phase and one device pair 180° out of phase).

Figure 8-10 shows the output of SYNC1 and SYNC2 of the primary device. The SYNC1 to SW delay (tSYNC_D) is not shown. This delay is generally not critical when secondary devices are synchronized to the primary device as they all have similar input and output delays.

TPS7H4011-SP SYNC1 and SYNC2 Output in Primary Device (Without SYNC1 to SW Delay Shown) Figure 8-10 SYNC1 and SYNC2 Output in Primary Device (Without SYNC1 to SW Delay Shown)

The SYNC1 and SYNC2 output are connected to the secondary devices to provide proper synchronization. Figure 8-11 shows the configuration and waveforms for four devices in parallel.

TPS7H4011-SP Parallel Operation With Four Devices Figure 8-11 Parallel Operation With Four Devices

Figure 8-12 shows the configuration and waveforms for three devices in parallel.

TPS7H4011-SP Parallel Operation With Three Devices Figure 8-12 Parallel Operation With Three Devices

Figure 8-13 shows the configuration and waveforms for two devices in parallel.

TPS7H4011-SP Parallel Operation With Two Devices Figure 8-13 Parallel Operation With Two Devices

Figure 8-14 shows a simplified schematic of two devices in parallel. Tie together the signals colored blue for parallel operation. See Section 9.2.4 for additional information.

TPS7H4011-SP Simplified Parallel Schematic Figure 8-14 Simplified Parallel Schematic